Philips Semiconductors Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
4
V
DD
SR02358
CLOCK
DATA
STROBE
RF/MAINin+
RF/MAINin–
REFin+
REFin–
IF/AUXin
TEST
LOAD SIGNALS
ADDRESS DECODER
2–BIT SHIFT
REGISTER
22–BIT SHIFT
REGISTER
CONTROL
LATCH
LATCH
MAIN DIVIDER
SM
REFERENCE
DIVIDER
2222
LATCH
AMP
AMP
16
17
5
4
20
19
18
11
23
LATCH
AUX DIVIDER
PHASE
DETECTOR
PHASE
DETECTOR
PUMP
BIAS
PUMP
CURRENT
SETTING
14
V
DDCP
GND
pre
3
SA
6, 9
24
GND
CP
R
SET
PHP
PHI
LOCK
PHA
15
7
8
22
10
PON
21
GND
2
V
DDpre
1
LOCK
SELECT
FRAC
COMP
Figure 4. Block Diagram (HBCC24)
HBCC24 PIN DESCRIPTION
SYMBOL PIN DESCRIPTION
V
DDPre
1 Prescaler supply voltage
GND 2 Digital ground
GND
Pre
3 Prescaler ground
RFin+ 4 RF input to main divider
RFin– 5 RF input to main divider
GND
CP
6 Charge pump ground
PHP 7 Main normal charge pump
PHI 8 Main integral charge pump
GND
CP
9 Charge pump ground
PHA 10 Auxiliary charge pump output
AUXin 11 Input to auxiliary divider
N/C 12 Not connected
N/C 13 Not connected
SYMBOL PIN DESCRIPTION
V
DDCP
14 Charge pump supply voltage
R
SET
15 External resistor from this pin to ground
sets the charge pump current
REFin– 16 Reference input
REFin+ 17 Reference input
CLOCK 18 Programming bus clock input
DATA 19 Programming bus data input
STROBE 20 Programming bus enable input
PON 21 Power down control
LOCK 22 Lock detect output
TEST 23 Test (should be either grounded or
connected to V
DD
)
V
DD
24 Digital supply
Philips Semiconductors Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
5
Limiting values
SYMBOL PARAMETER MIN. MAX. UNIT
V
DD
Digital supply voltage –0.3 +3.6 V
V
DDCP
Analog supply voltage –0.3 +3.6 V
(V
DDCP
–V
DD
) Difference in voltage between V
DDCP
and
V
DD
(V
DDCP
V
DD
) –0.3 +0.9 V
Vi
n
All input pins –0.3 V
DD
+ 0.3 V
V
GND
Difference in voltage between GND
CP
and GND (these pins should be
connected together)
–0.3 +0.3 V
T
stg
Storage temperature –55 +125 °C
T
amb
Operating ambient temperature –40 +85 °C
T
j
Maximum junction temperature 150 °C
Thermal characteristics
SYMBOL PARAMETER VALUE UNIT
R
th
j–a
Thermal resistance from junction to ambient in free air 135 K/W
Philips Semiconductors Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
6
CHARACTERISTICS
V
DDCP
= V
DD
= +3.0 V, T
amb
= +25 °C; unless otherwise specified.
SYMBOL
PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
DD
Digital supply voltage 2.7 3.6 V
V
DDCP
Analog supply voltage V
DDCP
w
V
DD
2.7 3.6 V
I
Total
Synthesizer operational supply current V
DD
= +3.0 V
(with main and aux on)
7.7 mA
I
Standby
Total supply current in power-down mode logic levels 0 or VDD 1 µA
RFin main divider input
f
VCO
VCO input frequency 500 2500 MHz
V
RFin
AC-coupled input signal level R
in
(external) = R
s
= 50 ;
sin
g
le-ended drive;
–18 0 dBm
g
max. limit is indicative
@ 500 to 2500 MHz
80 632 mV
PP
Z
RFin
Input impedance (real part) f
VCO
= 2.4 GHz 300
C
RFin
Typical pin input capacitance f
VCO
= 2.4 GHz 1 pF
N
main
Main divider ratio 512 65535
f
PCmax
Maximum loop comparison frequency indicative, not tested 4 MHz
AUX divider input
f
AUXin
Input frequency range 100 550 MHz
V
AC cou
p
led in
p
ut signal level
R
in
(external) = R
S
= 50 ;
–15 0 dBm
V
AUXin
AC
-
co
u
pled
inp
u
t
signal
le
v
el
in
()
S
max. limit is indicative
112 632 mV
PP
Z
AUXin
Input impedance (real part) f
VCO
= 500 MHz 3.9 k
C
AUXin
Typical pin input capacitance f
VCO
= 500 MHz 0.5 pF
N
AUX
Auxiliary division ratio 128 16383
Reference divider input
f
REFin
Input frequency range from TCXO 5 40 MHz
V
REFin
AC-coupled input signal level single-ended drive;
max. limit is indicative
360 1300 mV
PP
Z
REFin
Input impedance (real part) f
REF
= 20 MHz 10 k
C
REFin
Typical pin input capacitance f
REF
= 20 MHz 1 pF
R
REF
Reference division ratio SA = SM = ”000” 4 1023
Charge pump current setting resistor input
R
SET
External resistor from pin to ground 6 7.5 15 k
V
SET
Regulated voltage at pin R
SET
= 7.5 k 1.22 V
Charge pump outputs; R
SET
= 7.5 k
I
CP
Charge pump current ratio to I
SET
1
Current gain = I
PH
/I
SET
–15 +15 %
I
MATCH
Sink-to-source current matching V
PH
= 1/2 V
DDCP
–10 +10 %
I
ZOUT
Output current variation versus V
PH
2
V
PH
in compliance range –10 +10 %
I
LPH
Charge pump off leakage current V
PH
= 1/2 V
DDCP
–10 +10 nA
V
PH
Charge pump voltage compliance 0.6 V
DDCP
–0.7 V

SA8027DH,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC N/IF FREG SYNTHESIZER 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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