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AD7663ASTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
REV. B
AD7663
–15–
Voltage Reference Input
The AD7663 uses an external 2.5 V voltage reference.
The voltage reference input REF of the AD7663 has a dynamic
input impedance; it should therefore be driven by a low impedance
source with an efficient decoupling between REF and REFGND
inputs. This decoupling depends on the choice of the voltage
reference but usually consists of a 1 µF ceramic capacitor and a
low ESR tantalum capacitor connected to the REF and REFGND
inputs with minimum parasitic inductance. 47 µF is an appropriate
value for the tantalum capacitor when used with one of the
recommended reference voltages:
•
The low noise, low temperature drift ADR421 and AD780
voltage reference
•
The low power ADR291 voltage reference
•
The low cost AD1582 voltage reference
For applications using multiple AD7663s, it is more effective to
buffer the reference voltage with a low noise, very stable op amp
like the AD8031.
Care should also be taken with the reference temperature coefficient
of the voltage reference that directly affects the full-scale accu-
racy if this parameter matters. For instance, a ±15 ppm/°C
tempco of the reference changes the full scale by ±1 LSB/°C.
Note that V
REF
, as mentioned in the Specification tables, could be
increased to AVDD – 1.85 V. The benefit here is the increased
SNR obtained as a result of this increase. Since the input range is
defined in terms of V
REF
, this would essentially increase the ±REF
range from ±2.5 V to ±3 V and so on with an AVDD above
4.85 V. The theoretical improvement as a result of this increase
in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical
quantization noise, however, the observed improvement is approxi-
mately 1 dB. The AD780 can be selected with a 3 V reference
voltage.
Scaler Reference Input (Bipolar Input Ranges)
When using the AD7663 with bipolar input ranges, the connection
diagram in Figure 5 shows a reference buffer amplifier. This
buffer amplifier is required to isolate the REF pin from the signal
dependent current in the INx pin. A high speed op amp, such as
the AD8031, can be used with a single 5 V power supply with-
out degrading the performance of the AD7663. The buffer must
have good settling characteristics and provide low total noise
within the input bandwidth of the AD7663.
Power Supply
The AD7663 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and DVDD
+ 0.3 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from the
analog supply as shown in Figure 5. The AD7663 is independent
of power supply sequencing, once OVDD does not exceed DVDD
by more than 0.3 V, and thus free from supply voltage induced
latch-up. Additionally, it is very insensitive to power supply
variations over a wide frequency range as shown in Figure 9.
110
105
100
95
90
85
80
75
70
65
60
55
50
1 10 100 1000
PSRR – dB
FREQUENCY – kHz
Figure 9. PSRR vs. Frequency
POWER DISSIPATION
The AD7663 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power savings when the conversion rate is reduced as shown in
Figure 10. This feature makes the AD7663 ideal for very low
power battery applications.
This does not take into account the power, if any, dissipated by
the input resistive scaler that depends on the input voltage range
used and the analog input voltage even in power-down mode.
There is no power dissipated when the 0 V to 2.5 V is used or
when both the analog input voltage is 0V and a unipolar range,
0V to 5 V or 0 V to 10 V, is used.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
REV. B
AD7663
–16–
SAMPLING RATE – SPS
100k
1
POWER DISSIPATION – ␮W
10k
1k
100
10
1
0.1
10 100 1k 10k 100k 1M
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7663 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion is
complete. The CNVST signal operates independently of CS and
RD signals.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE CONVERT ACQUIRE CONVERT
Figure 11. Basic Conversion Timing
For a true sampling application, the recommended operation of
the CNVST signal is the following.
CNVST must be held HIGH from the previous falling edge of
BUSY and during a minimum delay corresponding to the acquisi-
tion time t
8
. Then, when CNVST is brought LOW, a conversion is
initiated and the BUSY signal goes HIGH until the completion
of the conversion. Although CNVST is a digital signal, it should
be designed with special care with fast, clean edges, and levels
with minimum overshoot and undershoot or ringing. It is a good
thing to shield the CNVST trace with ground and also to add a
low value serial resistor (i.e., 50 W) termination close to the output
of the component that drives this line. For applications where
the SNR is critical, the CNVST signal should have a very low
jitter. To achieve this, some use a dedicated oscillator for
CNVST generation, or at least to clock it with a high frequency,
low jitter clock as shown in Figure 5.
For other applications, conversions can be automatically initiated.
If CNVST is held low when BUSY is low, the AD7663 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping CNVST low, the AD7663 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7663 could sometimes
run slightly faster than the guaranteed limit of 250 kSPS.
t
9
t
8
RESET
DATA BUS
BUSY
CNVST
Figure 12. RESET Timing
DIGITAL INTERFACE
The AD7663 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7663 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7663
to the host system interface digital supply. Finally, by using the
OB/2C input pin, twos complement and straight binary coding
can be used.
The two signals CS and RD control the interface. When at least
one of these signals is HIGH, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7663 in
multicircuit applications and is held LOW in a single AD7663
design. RD is generally used to enable the conversion result on
the data bus.
t
1
t
3
t
4
t
11
CNVST
BUSY
DATA BUS
CS = RD = 0
t
10
PREVIOUS CONVERSION DATA NEW DATA
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
REV. B
AD7663
–17–
PARALLEL INTERFACE
The AD7663 is configured to use the parallel interface when
the SER/PAR is held LOW. The data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion as shown, respectively, in
Figures 14 and 15. When the data is read during the conversion,
however, it is recommended that it be read-only during the
first half of the conversion phase. That avoids any potential
feedthrough between voltage transients on the digital interface and
the most critical analog conversion circuitry.
RD
BUSY
CS
CURRENT
CONVERSION
DATA BUS
t
12
t
13
Figure 14. Slave Parallel Data Timing for Reading (Read
after Convert)
t
1
CS = 0
CNVST,
RD
PREVIOUS
CONVERSION
t
3
t
12
t
13
t
4
BUSY
DATA BUS
Figure 15. Slave Parallel Data Timing for Reading (Read
during Convert)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is LOW.
When BYTESWAP is HIGH, the LSB and MSB are swapped
and the LSB is output on D[15:8] and the MSB is output on
D[7:0]. By connecting BYTESWAP to an address line, the 16
data bits can be read in two bytes on either D[15:8] or D[7:0].
CS
BYTE
PINS D[15:8]
HI-Z
HIGH BYTE LOW BYTE
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t
12
t
12
t
13
RD
PINS D[7:0]
Figure 16. 8-Bit Parallel Interface
SERIAL INTERFACE
The AD7663 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7663 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7663 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. It also generates
a SYNC signal to indicate to the host when the serial data is valid.
The serial clock SCLK and the SYNC signal can be inverted if
desired. Depending on RDC/SDIN input, the data can be read
after each conversion or during the following conversion. Figures 17
and 18 show the detailed timing diagrams of these two modes.
Usually, because the AD7663 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. That makes the mode master, read after conversion,
the most recommended Serial Mode when it can be used.
In Read-during-Conversion Mode, the serial clock and data
toggle at appropriate instants that minimize potential feedthrough
between digital activity and the critical conversion decisions.
In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width. In this mode, if neces-
sary, the internal clock can be slowed down by a ratio selected
by the DIVSCLK inputs according to Table II.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7663ASTZ

Mfr. #:
Buy AD7663ASTZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit Bipolar 250kSPS CMOS
Lifecycle:
New from this manufacturer.
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