MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
16 ______________________________________________________________________________________
Serial Programming Interface
A serial interface programs the MAX19516 control reg-
isters through the CS, SDIN, and SCLK inputs. Serial
data is shifted into SDIN on the rising edge of SCLK
when CS is low. The MAX19516 ignores the data pre-
sented at SDIN and SCLK when CS is high.
CCSS
must
transition high after each read/write operation. SDIN
also serves as the serial-data output for reading control
registers. The serial interface supports two-byte transfer
in a communication cycle. The first byte is a control
byte, containing the address and read/write instruction,
written to the MAX19516. The second byte is a data
byte and can be written to or read from the MAX19516.
Figure 6 shows a serial-interface communication cycle.
The first SDIN bit clocked in establishes the communi-
cation cycle as either a write or read transaction (0 for
write operation and 1 for read operation). The following
7 bits specify the address of the register to be written or
read. The final 8 SDIN bits are the register data. All
address and data bits are clocked in or out MSB first.
During a read operation, the MAX19516 serial port dri-
ves read data (D7) into SDIN after the falling edge of
SCLK following the 8th rising edge of SCLK. Since the
minimum hold time on SDIN input is zero, the master
can stop driving SDIN any time after the 8th rising edge
of SCLK. Subsequent data bits are driven into SDIN on
the falling edge of SCLK. Output data in a read opera-
tion is latched on the rising edge of SCLK. Figure 7
shows the detailed serial-interface timing diagram.
R/W A6 A4A5 A2A3 A0A1 D7 D6 D4D5 D2D3 D0D1
R/W
0 = WRITE
1 = READ
CS
SCLK
SDIN
ADDRESS
DATA
WRITE OR READ
CS
t
CSS
t
CSH
t
SDD
t
SDS
t
SDH
t
SCLK
SCLK
SDIN
WRITE READ
Figure 6. Serial-Interface Communication Cycle
Figure 7. Serial-Interface Timing Diagram
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
______________________________________________________________________________________ 17
BIT NO. VALUE DESCRIPTION
7 0 Reserved
6 0 Reserved
5 0 or 1 1 = ROM read in progress
4 0 or 1 1 = ROM read completed and register data is valid (checksum is OK)
3 0 Reserved
2 1 Reserved
1 0 or 1 Reserved
0 0 or 1 1 = Duty-cycle equalizer DLL is locked
Table 2. Register 0Ah Status Byte
ADDRESS POR DEFAULT FUNCTION
00h 00000011 Power management
01h 00000000 Output format
02h 00000000 Digital output power management
03h 10110110 Data/DCLK timing
04h 00000000 C H A d ata outp ut ter m i nati on contr ol
05h 00000000 C H B d ata outp ut ter m i nati on contr ol
06h 00000000 C l ock d i vi d e/d ata for m at/test p atter n
07h Reserved Reserved—do not use
08h 00000000 Common mode
0Ah Software reset
Table 3. User-Programmable Registers
Register address 0Ah is a special-function register.
Writing data 5Ah to register 0Ah initiates a register
reset. When this operation is executed, all control regis-
ters are reset to default values. A read operation of reg-
ister 0Ah returns a status byte with information
described in Table 2.
The SHDN input (pin 7) toggles between any two
power-management states. The Power Management
register defines each power-management state. In the
default state, SHDN = 1 shuts down the MAX19516 and
SHDN = 0 returns to full power.
User-Programmable Registers
Power Management (00h)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
HPS_SHDN1 STBY_SHDN1 C H B_ON _S H D N 1C H A_O N _S H D N 1 HPS_SHDN0 STBY_SHDN0 CHB_ON_SHDN0 C H A_O N _S H D N 0
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
18 ______________________________________________________________________________________
HPS_SHDN0 STBY_SHDN0 CHA_ON_SHDN0 CHB_ON_SHDN0 SHDN INPUT = 0*
HPS_SHDN1 STBY_SHDN1 CHA_ON_SHDN1 CHB_ON_SHDN1 SHDN INPUT = 1**
X 0 0 0 Complete power-down
0 0 0 1 Channel B active, channel A full power-down
0 0 1 0 Channel A active, channel B full power-down
0 X 1 1 Channels A and B active
0 1 0 0 Channels A and B in standby mode
0 1 0 1 Channel B active, channel A standby
0 1 1 0 Channel A active, channel B standby
1 1 0 0 Channels A and B in standby mode
1 X X 1 Channels A and B active, output is averaged
1 X 1 X Channels A and B active, output is averaged
Control Bits:
Output Format (01h)
In addition to power management, the HPS_SHDN1
and HPS_SHDN0 activate an A+B adder mode. In this
mode, the results from both channels are averaged.
The MUX_CH bit selects which bus the (A+B)/2 data is
presented.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 BIT_ORDER_B BIT_ORDER_A MUX_CH MUX 0
*
HPS_SHDN0, STBY_SHDN0, CHA_ON_SHDN0, and CHB_ON_SHDN0 are active when SHDN = 0.
**
HPS_SHDN1, STBY_SHDN1, CHA_ON_SHDN1, and CHB_ON_SHDN1 are active when SHDN = 1.
X = Don’t care.
Note: When HPS_SHDN_ = 1 (A+B adder mode), CHA_ON_SHDN_ and CHB_ON_SHDN_ must BOTH equal 0 for power-down or
standby.
Bit 7, 6, 5 Set to 0 for proper operation
Bit 4 BIT_ORDER_B: Reverse CHB output bit order
0 = Defined data bus pin order (default)
1 = Reverse data bus pin order
Bit 3 BIT_ORDER_A: Reverse CHA output bit order
0 = Defined data bus pin order (default)
1 = Reverse data bus pin order
Bit 2 MUX_CH: Multiplexed data bus selection
0 = Multiplexed data output on CHA (CHA data presented first, followed by CHB data) (default)
1 = Multiplexed data output on CHB (CHB data presented first, followed by CHA data)
Bit 1 MUX: Digital output mode
0 = Dual data bus output mode (default)
1 = Single multiplexed data bus output mode
MUX_CH selects the output bus
Bit 0 Set to 0 for proper operation

MAX19516ETM+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 2Ch 100Msps 1.8V Precision ADC
Lifecycle:
New from this manufacturer.
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