MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
______________________________________________________________________________________ 31
Applications Information
Analog Inputs
Transformer-Coupled Differential Analog Input
The MAX19516 provides better SFDR and THD with
fully differential input signals than a single-ended input
drive. In differential input mode, even-order harmonics
are lower as both inputs are balanced, and each of the
ADC inputs only require half the signal swing compared
to single-ended input mode.
An RF transformer (Figure 18) provides an excellent
solution for converting a single-ended signal to a fully
differential signal. Connecting the center tap of the
transformer to CM_ provides a common-mode voltage.
The transformer shown has an impedance ratio of 1:1.4.
Alternatively, a different step-up transformer can be
selected to reduce the drive requirements. A reduced
signal swing from the input driver can also improve the
overall distortion. The configuration of Figure 18 is good
for frequencies up to Nyquist (f
CLK
/2).
Figure 17. Integrated Voltage Regulator
IN
2.3V TO 3.5V
ENABLE
OUT
1.8V
REGULATOR
REFERENCE
INTERNAL
ANALOG
CIRCUITS
AVDD
(PINS 1, 12, 13, 48)
GND
Figure 19. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
1
5
3
6
2
4
N.C.
V
IN
0.1µF
T1
MINI-CIRCUITS
ADT1-1WT
IN_+
CM_
IN_-
N.C.
1
5
3
6
2
4
N.C.
T2
MINI-CIRCUITS
ADT1-1WT
N.C.
75
0.5%
75
0.5%
110
0.5%
110
0.5%
0.1µF
MAX19516
Figure 18. Transformer-Coupled Input Drive for Input
Frequencies Up to Nyquist
MAX19516
1
5
3
6
2
4
N.C. N.C.
V
IN
0.1µF
T1
MINI-CIRCUITS
ADT1-1WT
36.5
0.5%
36.5
0.5%
0.1µF
IN_+
CM_
IN_-
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
32 ______________________________________________________________________________________
The circuit of Figure 19 also converts a single-ended
input signal to a fully differential signal. Figure 19 uti-
lizes an additional transformer to improve the common-
mode rejection allowing high-frequency signals beyond
the Nyquist frequency. A set of 75 and 110 termina-
tion resistors provide an equivalent 50 termination to
the signal source. The second set of termination resis-
tors connect to CM_ providing the correct input com-
mon-mode voltage.
Single-Ended AC-Coupled Input Signal
Figure 20 shows a single-ended, AC-coupled input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity. Bias voltage is applied to the
inputs through internal 2k resistors. See Common
Mode register 08h for further details.
DC-Coupled Input
The MAX19516’s wide common-mode voltage range
(0.4V to 1.4V) allows DC-coupled signals. Ensure that the
common-mode voltage remains between 0.4V and 1.4V.
Clock Input
Figure 21 shows a single-ended-to-differential clock
input converting circuit.
Grounding, Bypassing, and
Board-Layout Considerations
The MAX19516 requires high-speed board-layout
design techniques. Locate all bypass capacitors as
close as possible to the device, preferably on the same
side as the ADC, using surface-mount devices for mini-
mum inductance. Bypass AVDD, OVDD, REFIO, CMA,
and CMB with 0.1µF ceramic capacitors to GND.
Multilayer boards with ground and power planes
produce the highest level of signal integrity. Route high-
speed digital signal traces away from the sensitive ana-
log traces of either channel. Make sure to isolate the
analog input lines to each respective converter to mini-
mize channel-to-channel crosstalk. Keep all signal lines
short and free of 90° turns.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a best-fit straight line. Worst-case deviation is
defined as INL.
Differential Nonlinearity (DNL)
DNL is the difference between the measured transfer
function step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. DNL
deviations are measured at each step of the transfer
function and the worst-case deviation is defined as DNL.
Offset Error
Offset error is a parameter that indicates how well the
actual transfer function matches the ideal transfer func-
tion at midscale. Ideally, the midscale transition occurs
at 0.5 LSB above midscale. The offset error is the
amount of deviation between the measured midscale
transition point and the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the measured transfer function matches the
slope of the ideal transfer function based on the speci-
fied full-scale input-voltage range. The gain error is
defined as the relative error of the measured transfer
function and is expressed as a percentage.
Figure 20. Single-Ended, AC-Coupled Input Drive
MAX19516
0.1µF
100
100
0.1µF
IN_+
CM_
0.1µF
IN_-
MAX4108
V
IN
Figure 21. Single-Ended-to-Differential Clock Input
MAX19516
49.9
49.9
0.01µF
0.1µF
0.01µF
CLK+
CLK-
CLKIN
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
______________________________________________________________________________________ 33
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the
Nyquist band for small-signal inputs. The DC offset is
excluded from this noise calculation. For this converter, a
small signal is defined as a single tone with an amplitude
less than -35dBFS. This parameter captures the thermal
and quantization noise characteristics of the converter
and can be used to help calculate the overall noise figure
of a receive channel. Refer to www.maxim-ic.com for
application notes on Thermal + Quantization Noise Floor.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR
[max]
= 6.02 x N + 1.76
In reality, there are other noise sources besides quanti-
zation noise (e.g., thermal noise, reference noise, clock
jitter, etc.). SNR is computed by taking the ratio of the
RMS signal to the RMS noise. RMS noise includes all
spectral components to the Nyquist frequency exclud-
ing the fundamental, the first six harmonics (HD2–HD7),
and the DC offset.
Signal-to-Noise and Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus the RMS distortion. RMS
noise includes all spectral components to the Nyquist
frequency excluding the fundamental, the first six har-
monics (HD2–HD7), and the DC offset. RMS distortion
includes the first six harmonics (HD2–HD7).
Single-Tone Spurious-Free Dynamic Range
(SFDR1 and SFDR2)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS amplitude of the next largest spurious
component, excluding DC offset. SFDR1 reflects the
spurious performance based on worst 2nd-order or
3rd-order harmonic distortion. SFDR2 is defined by the
worst spurious component excluding 2nd- and 3rd-
order harmonics and DC offset.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS of the first six harmonics of
the input signal to the fundamental itself. This is
expressed as:
where V
1
is the fundamental amplitude and V
2
–V
7
are
the amplitudes of the 2nd-order through 7th-order
harmonics (HD2–HD7).
Third-Order Intermodulation (IM3)
IM3 is the total power of the third-order intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones f
IN1
and f
IN2
. The
individual input tone levels are at -7dBFS. The third-
order intermodulation products are: 2 x f
IN1
- f
IN2
, 2 x
f
IN2
- f
IN1
, 2 x f
IN1
+ f
IN2
, 2 x f
IN2
+ f
IN1
.
Aperture Delay
The input signal is sampled on the rising edge of the
sampling clock. There is a small delay between the ris-
ing edge of the sampling clock and the actual sampling
instant, which is defined as aperture delay (t
AD
).
Aperture Jitter
Aperture jitter (t
AJ
) is defined as the sample-to-sample
time variation in the aperture delay.
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The specified overdrive recovery time is
measured with an input transient that exceeds the full-
scale limits by ±10%.
Chip Information
PROCESS: CMOS
THD
VVVVVV
V
log
+++++
20
2
2
3
2
4
2
5
2
6
2
7
2
1
SINAD
NOISE DISTORTION
SIGNAL
RMS RMS
RMS
log
+
20
22
SNR
SIGNAL
NOISE
RMS
RMS
log
20

MAX19516ETM+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 2Ch 100Msps 1.8V Precision ADC
Lifecycle:
New from this manufacturer.
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