Clock Inputs
The input clock interface provides for flexibility in the
requirements of the clock driver. The MAX19516
accepts a fully differential clock or single-ended logic-
level clock. For differential clock operation, connect a
differential clock to the CLK+ and CLK- inputs. In this
mode, the input common mode is established internally
to allow for AC-coupling. The differential clock signal
can also be DC-coupled if the common mode is con-
strained to the specified 1V to 1.4V clock input com-
mon-mode range. For single-ended operation, connect
CLK- to GND and drive the CLK+ input with a logic-
level signal. When the CLK- input is grounded (or
pulled below the threshold of the clock mode detection
comparator) the differential-to-single-ended conversion
stage is disabled and the logic-level inverter path is
activated.
Clock Divider
The MAX19516 offers a clock-divider option. Enable
clock division either by setting DIV0 and DIV1 through
the serial interface; see the Clock Divide/Data
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
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Figure 8. Simplified Clock Input Schematic
