10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 100MHz, A
IN
= -0.5dBFS, data output termina-
tion = 50, T
A
= +25°C, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
MAX19516 toc19
2.3 2.5 2.7 2.9 3.1 3.3 3.5
64.0
64.5
65.0
65.5
66.0
66.5
67.0
67.5
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
MAX19516 toc20
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT (mA)
60 65 70 75 80 85 90 95 100 105 110
0
2
4
6
8
10
12
14
16
18
20
V
OVDD
= 1.8V
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT (mA)
MAX19516 toc21
60 65 70 75 80 85 90 95 100 105 110
0
10
5
15
20
25
30
35
40
V
OVDD
= 3.6V
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT (mA)
MAX19516 toc22
-40-200 20406080
15
17
19
21
23
25
27
29
31
33
35
V
OVDD
= 3.6V
V
OVDD
= 1.8V
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX19516 toc23
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
0
5
10
15
20
25
30
DUAL BUS
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX19516 toc24
1.7 2.5 2.92.1 2.71.9 2.3 3.1 3.53.3
0
15
20
5
10
30
35
40
25
45
50
MULTIPLEXED BUS
PERFORMANCE vs. CLOCK DUTY CYCLE
CLOCK DUTY CYCLE (%)
PERFORMANCE (dBFS)
MAX19516 toc25
30 6040 50 5545 6535
55
60
65
75
80
85
70
90
95
SFDR1
SINAD
SFDR2
SNR
-THD
PERFORMANCE vs. TEMPERATURE
TEMPERATURE (°C)
PERFORMANCE (dBFS)
MAX19516 toc26
-40 40200-20 8060
50
65
75
80
85
70
55
60
90
95
SFDR1
SINAD
SFDR2
SNR
-THD
GAIN ERROR vs. TEMPERATURE
TEMPERATURE (°C)
GAIN ERROR (%)
MAX19516 toc27
-40 40200-20 8060
-0.05
-0.01
0.01
0.02
0.03
0
-0.03
-0.04
-0.02
0.04
0.05
Typical Operating Characteristics (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 100MHz, A
IN
= -0.5dBFS, data output termina-
tion = 50, T
A
= +25°C, unless otherwise noted.)
COMMON-MODE REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
COMMON-MODE REFERENCE VOLTAGE (V)
MAX19516 toc30
-40 40200-20 8060
0
1.2
0.8
0.4
0.2
1.4
1.0
0.6
1.6
V
CM
= 1.35V
V
CM
= 1.2V
V
CM
= 0.9V
V
CM
= 0.6V
V
CM
= 0.75V
V
CM
= 0.45V
V
CM
= 1.05V
OFFSET ERROR vs. TEMPERATURE
TEMPERATURE (°C)
OFFSET ERROR (mV)
MAX19516 toc28
-40 40200-20 8060
-0.7
-0.3
-0.1
0
0.1
-0.2
-0.5
-0.6
-0.4
0.2
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
______________________________________________________________________________________ 11
REFERENCE VOLTAGE vs. TEMPERATURE
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX19516 toc29
-40 40200-20 8060
1.2432
1.2495
1.2474
1.2453
1.2516
GAIN ERROR vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
GAIN ERROR (%)
MAX19516 toc31
1.6 2.6 3.42.4 3.23.02.82.01.8 3.62.2
-0.08
-0.06
-0.04
0
0.02
0.04
-0.02
0.06
0.08
REGULATOR MODE
INPUT CURRENT
vs. COMMON-MODE VOLTAGE
COMMON-MODE VOLTAGE (V)
INPUT CURRENT (µA)
MAX19516 toc32
0.4 0.9 1.30.8 1.21.11.00.60.5 1.40.7
30
40
60
70
50
80
90
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
12 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 12, 13, 48 AVDD Analog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1µF.
2 CMA Channel A Common-Mode Input-Voltage Reference
3 INA+ Channel A Positive Analog Input
4 INA- Channel A Negative Analog Input
5 SPEN Active-Low SPI Enable. Drive high to enable parallel programming mode.
6 REFIO
Reference Input/Output. To use internal reference, bypass to GND with a > 0.1µF capacitor. See
the Reference Input/Output (REFIO) section for external reference adjustment.
7 SHDN
Active-High Power-Down. If SPEN is high (parallel programming mode), a register reset is initiated
on the falling edge of SHDN.
8 I.C. Internally Connected. Leave unconnected.
9 INB+ Channel B Positive Analog Input
10 INB- Channel B Negative Analog Input
11 CMB Channel B Common-Mode Input-Voltage Reference
14 SYNC Clock-Divider Mode Synchronization Input
15 CLK+ Clock Positive Input
16 CLK-
Clock Negative Input. If CLK- is connected to ground, CLK+ is a single-ended logic-level clock
input. Otherwise, CLK+/CLK- are self-biased differential clock inputs.
17, 18 GND Ground. Connect all ground inputs and EP (exposed pad) together.
19 DORB Channel B Data Over Range
20 DCLKB Channel B Data Clock
21 D0B Channel B Three-State Digital Output, Bit 0 (LSB)
22 D1B Channel B Three-State Digital Output, Bit 1
23 D2B Channel B Three-State Digital Output, Bit 2
24 D3B Channel B Three-State Digital Output, Bit 3
25, 36 OVDD Digital Supply Voltage. Bypass each OVDD input to GND with 0.1µF capacitor.
26 D4B Channel B Three-State Digital Output, Bit 4
27 D5B Channel B Three-State Digital Output, Bit 5
28 D6B Channel B Three-State Digital Output, Bit 6
29 D7B Channel B Three-State Digital Output, Bit 7
30 D8B Channel B Three-State Digital Output, Bit 8
31 D9B Channel B Three-State Digital Output, Bit 9 (MSB)
32 D0A Channel A Three-State Digital Output, Bit 0 (LSB)
33 D1A Channel A Three-State Digital Output, Bit 1
34 D2A Channel A Three-State Digital Output, Bit 2
35 D3A Channel A Three-State Digital Output, Bit 3
37 D4A Channel A Three-State Digital Output, Bit 4
38 D5A Channel A Three-State Digital Output, Bit 5
39 D6A Channel A Three-State Digital Output, Bit 6

MAX19516ETM+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 2Ch 100Msps 1.8V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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