MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
20 ______________________________________________________________________________________
Data/DCLK Timing (03h)
Bit 7 DA_BYPASS: Data aligner bypass
0 = Nominal
1 = Bypasses data aligner delay line to minimize output data latency with respect to the input clock.
Rising clock to data transition is approximately 6ns with DTIME = 000b settings (default)
Bit 6 DLY_HALF_T: Data and DCLK delayed by T/2
0 = Normal, no delay (default)
1 = Delays data and DCLK outputs by T/2
Disabled in MUX data bus mode
Bit 5, 4, 3 DCLKTIME_2, DCLKTIME_1, DCLKTIME_0: DCLK timing adjust (controls both channels)
000 = Nominal
001 = +T/16
010 = +2T/16
011 = +3T/16
100 = Reserved, do not use
101 = -1T/16
110 = -2T/16 (default)
111 = -3T/16
Bit 2, 1, 0 DTIME_2, DTIME_1, DTIME_0: Data timing adjust (controls both channels)
000 = Nominal
001 = +T/16
010 = +2T/16
011 = +3T/16
100 = Reserved, do not use
101 = -1T/16
110 = -2T/16 (default)
111 = -3T/16
