OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MAX19516ETM+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 100MHz, A
IN
= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERCHANNEL CHARACTERISTICS
f
INA
or f
INB
= 70MHz at -1dBFS 95
Crosstalk
f
INA
or f
INB
= 175MHz at -1dBFS 85
dBc
Gain Match f
IN
= 70MHz ±0.05 dB
Offset Match f
IN
= 70MHz ±0.1 %FSR
Phase Match f
IN
= 70MHz ±0.5 D eg r ees
ANALOG OUTPUTS (CMA, CMB)
CMA, CMB Output Voltage V
COM
Default programmable setting 0.85 0.9 0.95 V
INTERNAL REFERENCE
REFIO Output Voltage V
REFOUT
1.23 1.25 1.27 V
REFIO Temperature Coefficient TC
REF
< ±60 ppm/°C
EXTERNAL REFERENCE
REFIO Input-Voltage Range V
REFIN
1.25 +5/
-10%
V
REFIO Input Resistance R
REFIN
10
±20%
kΩ
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE
Differential Clock Input Voltage 0.4 to 2.0 V
P-P
Self-biased 1.2
Differential Input Common-Mode
Voltage
DC-coupled clock signal 1.0 to 1.4
V
Differential, default 10 kΩ
Differential, internal termination selected 100 ΩInput Resistance R
CLK
Common mode 9 kΩ
Input Capacitance C
CLK
To ground, each input 3 pF
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V
CLK-
< 0.1V)
Single-Ended Mode Selection
Threshold (V
CLK-
)
0.1 V
Allowable Logic Swing (V
CLK+
) 0 - V
AVDD
V
Single-Ended Clock Input High
Threshold (V
CLK+
)
1.5 V
Single-Ended Clock Input Low
Threshold (V
CLK+
)
0.3 V
V
CLK+
= V
AVDD
= 1.8V or 3.3V +0.5
Input Leakage (CLK+)
V
CLK+
= 0V -0.5
µA
Input Leakage (CLK-) V
CLK-
= 0V -150 -50 µA
Input Capacitance (CLK+) 3pF
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 100MHz, A
IN
= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLOCK INPUT (SYNC)
Allowable Logic Swing 0 - V
AVDD
V
Sync Clock Input High Threshold 1.5 V
Sync Clock Input Low Threshold 0.3 V
V
SYNC
= V
AVDD
= 1.8V or 3.3V +0.5
Input Leakage
V
SYNC
= 0V -0.5
µA
Input Capacitance 4.5 pF
DIGITAL INPUTS (SHDN, SPEN)
Allowable Logic Swing 0 - V
AVDD
V
Input High Threshold 1.5 V
Input Low Threshold 0.3 V
V
SHDN
/V
SPEN
= V
AVDD
= 1.8V or 3.3V +0.5
Input Leakage
V
SHDN
/V
SPEN
= 0V -0.5
µA
Input Capacitance C
DIN
3pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODE
Allowable Logic Swing 0 - V
AVDD
V
Input High Threshold 1.5 V
Input Low Threshold 0.3 V
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 1.8V or 3.3V +0.5
Input Leakage
V
SCLK
/V
SDIN
/V
CS
= 0V -0.5
µA
Input Capacitance C
DIN
3pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = V
AVDD
)—PARALLEL CONTROL MODE (Figure 5)
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 1.8V 7 12 17
Input Pullup Current
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 3.3V 16 21 26
µA
V
SCLK
/V
SDIN
/V
CS
= 0V, V
AVDD
= 1.8V -65 -50 -35
Input Pulldown Current
V
SCLK
/V
SDIN
/V
CS
= 0V, V
AVDD
= 3.3V -105 -90 -75
µA
V
AVDD
= 1.8V 1.35 1.45 1.55
Open-Circuit Voltage V
OC
V
AVDD
= 3.3V 2.58 2.68 2.78
V
DIGITAL OUTPUTS (75Ω, D0–D9 (A and B Channel), DCLKA, DCLKB, DORA, DORB)
Output-Voltage Low V
OL
I
SINK
= 200µA 0.2 V
Output-Voltage High V
OH
I
SOURCE
= 200µA
V
OVDD
- 0.2
V
V
OVDD
applied +0.5
Three-State Leakage Current I
LEAK
GND applied -0.5
µA
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 100MHz, A
IN
= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER-MANAGEMENT CHARACTERISTICS
Wake-Up Time from Shutdown t
WAKE
Internal reference, C
REFIO
= 0.1µF (10τ)5ms
Wake-Up Time from Standby t
WAKE
Internal reference 15 µs
SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)
SCLK Period t
SCLK
50 ns
SCLK to CS Setup Time t
CSS
10 ns
SCLK to CS Hold Time t
CSH
10 ns
SDIN to SCLK Setup Time t
SDS
Serial-data write 10 ns
SDIN to SCLK Hold Time t
SDH
Serial-data write 0 ns
SCLK to SDIN Output Data Delay t
SDD
Serial-data read 10 ns
TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9) (Default Timing, see Table 5)
Clock Pulse-Width High t
CH
5.0 ns
Clock Pulse-Width Low t
CL
5.0 ns
Clock Duty Cycle t
CH
/t
CLK
30 to 70 %
C
L
= 10pF, V
OVDD
= 1.8V (Note 2) 2.1 4.0 5.8
Data Delay After Rising Edge of
CLK+
t
DD
C
L
= 10pF, V
OVDD
= 3.3V 3.1
ns
Data to DCLK Setup Time t
SETUP
C
L
= 10pF, V
OVDD
= 1.8V (Note 2) 8.1 8.7 ns
Data to DCLK Hold Time t
HOLD
C
L
= 10pF, V
OVDD
= 1.8V (Note 2) 0.6 1.3 ns
TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10) (Default Timing, see Table 5)
Clock Pulse-Width High t
CH
5.0 ns
Clock Pulse-Width Low t
CL
5.0 ns
Clock Duty Cycle t
CH
/t
CLK
30 to 70 %
C
L
= 10pF, V
OVDD
= 1.8V (Note 2) 2.1 3.9 5.8
Data Delay After Rising Edge of
CLK+
t
DD
C
L
= 10pF, V
OVDD
= 3.3V 3.1
ns
Data to DCLK Setup Time t
SETUP
C
L
= 10pF, V
OVDD
= 1.8V (Note 2) 2.9 3.9 ns
Data to DCLK Hold Time t
HOLD
C
L
= 10pF, V
OVDD
= 1.8V (Note 2) 0.4 1.1 ns
DCLK Duty Cycle t
DCH
/t
CLK
C
L
= 10pF, V
OVDD
= 1.8V (Note 2) 41 50 59 %
MUX Data Duty Cycle t
CHA
/t
CLK
C
L
= 10pF, V
OVDD
= 1.8V (Note 2) 41 50 59 %
TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)
Setup Time for Valid Clock Edge t
SUV
Edge mode (Note 2) 0.7 ns
Hold-Off Time for Invalid Clock
Edge
t
HO
Edge mode (Note 2) 0.5 ns
Minimum Synchronization Pulse
Width
Relative to input clock period 2 Cycles
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

MAX19516ETM+T

Mfr. #:
Buy MAX19516ETM+T
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 2Ch 100Msps 1.8V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet