ZSSC3138
© 2016 Integrated Device Technology, Inc.
The ZSSC3138 supports a high sample rate ADC mode (2-step conversion) with the advantage of a much shorter
conversion time but with the drawback of a lower noise immunity caused by the shorter signal integration time.
The conversion time t
ADC,2step
in this mode is roughly calculated by equation (2):
(
)
=
+
2
f
2
t
OSC
2
3
r
step-
ADC,2
ADC
(2)
Refer to the ZSSC313x Bandwidth Calculation Sheet for a detailed calculation of sampling time and bandwidth.
The result of the A/D conversion is a relative counter result Z corresponding to the following equation:
)RS
V
V
(2Z
ADC_REF
ADC_DIFF
r
ADC
−⋅=
(3)
Where
r
ADC
Resolution of A/D conversion
V
ADC_DIFF
Differential ADC input voltage
V
ADC_REF
ADC reference voltage (V
VBR_T
-V
VBR_B
or V
VDDA
-V
VSSA
, if BRREF=1)
RS Digital ADC Range Shift (RS = 1/16, 1/8, 1/4, 1/2; controlled by the EEPROM contents)
With the RS value, a sensor input signal can be shifted in the optimal input range of the ADC.
The condition required for ensuring the specified accuracy, stability, and non-linearity parameters of the analog
front-end is that the differential ADC input voltage V
ADC_DIFF
does not exceed the range of 10% to 90% of the ADC
reference voltage V
ADC_REF
. This requirement must be met for the whole temperature range and for all sensor
tolerances.
