ZSSC3138
Datasheet
© 2016 Integrated Device Technology, Inc.
16
January 25, 2016
Table 2.3 ADC Resolution versus Output Resolution and Sample Rate
ADC Adjustment Output Resolution
1)
Sample Rate
2)
Averaged Bandwidth
2)
ADC
Sample
Rate Mode
r
ADC
[bit]
Digital
[bit]
Analog
[bit]
f
OSC
=3MHz
[Hz]
f
OSC
=4MHz
[Hz]
f
OSC
=3MHz
[Hz]
f
OSC
=4MHz
[Hz]
Normal
13 13 12 345 460 130 172
14 14 12 178 237 67 89
15 14 12 90 120 34 45
16 14 12 45 61 17 23
High
13 13 12 5859 7813 2203 2937
14 14 12 3906 5208 1469 1958
15 14 12 2930 3906 1101 1468
16 14 12 1953 2604 734 979
1) Output resolution does not exceed ADC resolution. PGA gain should be such that the differential ADC input signal uses at least 50% of ADC input
range to ensure maximum achievable output resolution.
2) Refer to the ZSSC313x Bandwidth Calculation Sheet for a detailed calculation of sampling time and bandwidth.
2.4. Temperature Measurement
The ZSSC3138 supports acquiring temperature data needed for conditioning of the sensor signal using an
internal pn-junction temperature sensor.
Refer to the ZSSC313x Functional Description for a detailed explanation of temperature sensor adaptation and
adjustment.
2.5. System Control and Conditioning Calculation
The system control supports the following tasks/features:
Managing the startup sequence
Controlling the measurement cycle regarding to the EEPROM-stored configuration data
Sensor signal conditioning (calculation of the 16-bit correction for each measurement signal using the
EEPROM-stored conditioning coefficients and the ROM-based formulas)
Processing communication requests received via the digital interfaces
Performing failsafe tasks and message detected errors by setting diagnostic states
2.5.1. General Working Modes
ZSSC3138 supports three different working modes:
Normal Operation Mode (NOM) – for continuous processing of signal conditioning
Command Mode (CM) – for calibration and access to all internal registers
Diagnostic Mode (DM) for failure messages
ZSSC3138
Datasheet
© 2016 Integrated Device Technology, Inc.
17
January 25, 2016
2.5.2. Startup Phase
1
After power-on, the startup phase is processed, which includes
Internal supply voltage settling including reset of the circuitry by the power-on reset block (POR).
Refer to the ZSSC313x High Voltage Protection Description for power-on/off thresholds.
Duration (beginning with V
VDDA
-V
VSSA
=0V): 500µs to 2ms; AOUT: high impedance.
System start and configuration, EEPROM readout, and signature check.
Duration: ~200µs; AOUT: lower diagnostic range (LDR).
Processing the measurement cycle start routine.
Duration: 5x A/D conversion time; AOUT behavior depends on configured one-wire communication mode
(refer to section 2.6):
OWIANA or OWIDIS AOUT: lower diagnostic range (LDR)
OWIWIN or OWIENA AOUT: tri-state
If an error is detected during the startup phase, the Diagnostic Mode (DM) is activated and the analog output at
the AOUT pin remains in the lower diagnostic range.
After the startup phase, the continuous running measurement and sensor signal conditioning cycle is started, and
analog or digital output of the conditioned sensor signal is activated. If the one-wire communication mode
OWIWIN is selected, the OWI startup window expires before analog output is available.
2.5.3. Conditioning Calculation
The digitalized value for the bridge signal is processed with a conditioning formula to remove offset and
temperature dependency and to compensate nonlinearity up to 3
rd
order. The result is a non-negative 15-bit value
for the measured bridge sensor signal in the range [0; 1). This value is available for readout via C or OWI
communication. For the analog output, the value is clipped to the programmed output limits.
Note: The extent of signal deviation that can be compensated by the conditioning calculation depends on the
specific sensor signal characteristics. For a rough estimation, assume the following: offset compensation
and gain correction are not limited. Notice that resolution of the digitally gained signal is determined by
the ADC resolution in respect to the dynamic input range used. The temperature correction includes first
and second order terms and should be adequate for all practically relevant cases. The non-linearity
correction of the sensor signal is possible for second-order up to about 30% FS regarding ideal fit and for
third-order up to about 20% FS. Overall, the conditioning formula applied is able to reduce the non-
linearity of the sensor signal by a factor of 10.
1
All timing values are roughly estimated for an oscillator frequency f
OSC
=3MHz and are proportional to that frequency.
ZSSC3138
Datasheet
© 2016 Integrated Device Technology, Inc.
18
January 25, 2016
2.6. Analog or Digital Output
The AOUT pin is used for analog output and for one-wire communication (OWI). The latter can be used for digital
readout of the conditioned sensor signal and for end-of-line sensor module calibration. The ZSSC3138 supports
different modes for the analog output in interaction with OWI communication:
OWIENA: Analog output is deactivated; OWI readout of the signal data is enabled.
OWIWIN: Analog output starts after the startup phase and after the OWI startup window if OWI
communication is not initiated; OWI communication for configuration or for end-of-line
calibration can be started during the OWI startup window (maximum ~500ms) by sending the
START_CM command.
OWIANA: Analog output starts after the startup phase; OWI communication for configuration or for end-
of-line calibration can be started during the OWI startup window (maximum ~500ms) by
sending the START_CM command; for command transmission, the driven analog output at
the AOUT pin must be overwritten by the external communication master (AOUT drive
capability is current-limited).
OWIDIS: Analog output starts after the startup phase; OWI readout of the signal data is disabled.
The analog output signal is driven by an offset compensated, rail-to-rail output buffer that is current-limited to
prevent damage to the ZSSC3138 from a short circuit between the analog output and power supply or ground.
Output resolution of at least 12-bit in the range of 10% to 90% FS is ensured by a 12.4-bit resistor string DAC.
2.7. Serial Digital Interface
The ZSSC3138 includes a serial digital I²C
TM
interface and a ZACwire
TM
interface for one-wire communication
(OWI). The digital interfaces allow configuration and calibration of the sensor module. OWI communication can be
used to perform an end-of-line calibration via the analog output pin AOUT of a completely assembled sensor
module. The interfaces also provide the readout of the conditioned sensor signal data during normal operation.
Refer to the ZSSC313x Functional Description for a detailed description of the serial interfaces and the
communication protocols.
2.8. Failsafe Features
The ZSSC3138 detects various failures. When a failure is detected, Diagnostic Mode (DM) is activated. DM is
indicated by setting the output pin AOUT to the Lower Diagnostic Range (LDR). When using digital serial
communication protocols (I²C or OWI) to read conditioning results data, the error status is indicated by a
specific error code.
A watchdog timer controls the proper operation of the microcontroller. The operation of the internal oscillator is
monitored by an oscillator-failure detection circuit. EEPROM and RAM content are checked when accessed.
Control registers are parity protected.
The sensor connection is checked with regard to broken wires or short circuits (sensor connection check, sensor
short check).
Refer to the ZSSC313x Functional Description for a detailed description of failsafe features and methods of error
indication.

ZSSC3138BA2R

Mfr. #:
Manufacturer:
IDT
Description:
Sensor Interface Sensor Signal Conditoner
Lifecycle:
New from this manufacturer.
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