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CAT140029TWI-G

P1-P3P4-P6P7-P9P10-P11
CAT140xx
http://onsemi.com
4
Table 6. ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
V
CC
= Full range, T
A
= −40°C to +85°C unless otherwise noted. Typical values at T
A
= +25°C and V
CC
= 5 V for L/M/J versions,
V
CC
= 3.3 V for T/S versions, V
CC
= 3 V for R version and V
CC
= 2.5 V for Z version.
Symbol
Parameter Threshold Conditions Min Typ Max Units
V
TH
Reset Threshold
Voltage
L
T
A
= +25°C 4.56 4.63 4.70
V
T
A
= −40°C to +85°C 4.50 4.75
M
T
A
= +25°C 4.31 4.38 4.45
T
A
= −40°C to +85°C 4.25 4.50
J
T
A
= +25°C 3.93 4.00 4.06
T
A
= −40°C to +85°C 3.89 4.10
T
T
A
= +25°C 3.04 3.08 3.11
T
A
= −40°C to +85°C 3.00 3.15
S
T
A
= +25°C 2.89 2.93 2.96
T
A
= −40°C to +85°C 2.85 3.00
R
T
A
= +25°C 2.59 2.63 2.66
T
A
= −40°C to +85°C 2.55 2.70
Z
T
A
= +25°C 2.28 2.32 2.35
T
A
= −40°C to +85°C 2.25 2.38
Symbol Parameter Conditions Min Typ
(Note 1)
Max Units
Reset Threshold Tempco 30 ppm/°C
t
RPD
V
CC
to Reset Delay (Note 2) V
CC
= V
TH
to (V
TH
−100 mV) 20
ms
t
PURST
Reset Active Timeout Period T
A
= −40°C to +85°C 140 240 460 ms
V
OL
RESET Output Voltage Low
(Push−pull, Active LOW,
CAT140xx9)
V
CC
= V
TH
min, I
SINK
= 1.2 mA
R/S/T/Z
0.3
V
V
CC
= V
TH
min, I
SINK
= 3.2 mA
J/L/M
0.4
V
CC
> 1.0 V, I
SINK
= 50 mA
0.3
V
OH
RESET Output Voltage High
(Push−pull, Active LOW,
CAT140xx9)
V
CC
= V
TH
max, I
SOURCE
= −500 mA
R/S/T/Z
0.8 V
CC
V
V
CC
= V
TH
max, I
SOURCE
= −800 mA
J/L/M
V
CC
− 1.5
V
OL
RESET Output Voltage Low
(Push−pull, Active HIGH,
CAT140xx1)
V
CC
> V
TH
max, I
SINK
= 1.2 mA
R/S/T/Z
0.3
V
V
CC
> V
TH
max, I
SINK
= 3.2 mA
J/L/M
0.4
V
OH
RESET Output Voltage High
(Push−pull, Active HIGH,
CAT140xx1)
1.8 V < V
CC
≤ V
TH
min,
I
SOURCE
= −150 mA
0.8 V
CC
V
1. Production testing done at T
A
= +25°C; limits over temperature guaranteed by design only.
2. RESET
output for the CAT140xx9; RESET output for the CAT140xx1.
CAT140xx
http://onsemi.com
5
PIN DESCRIPTION
RESET/RESET
: RESET OUTPUT
This output is available in two versions: CMOS Active Low
(CAT140xx9) and CMOS Active High (CAT140xx1). Both
versions are push−pull outputs for high efficiency.
SDA: SERIAL DATA ADDRESS
The Serial Data I/O pin receives input data and transmits
data stored in EEPROM. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is delivered
on the negative edge of SCL.
SCL: SERIAL CLOCK
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
A0, A1, A2: Device Address Inputs
The Address inputs set the device address when cascading
multiple devices. When not driven, these pins are pulled
LOW internally.
DEVICE OPERATION
The CAT140xx products combine the accurate voltage
monitoring capabilities of a standalone voltage supervisor
with the high quality and reliability of standard EEPROMs
from ON Semiconductor.
Reset Controller Description
The reset signal is asserted LOW for the CAT140xx9 and
HIGH for the CAT140xx1 when the power supply voltage
falls below the threshold trip voltage and remains asserted
for at least 140 ms (t
PURST
) after the power supply voltage
has risen above the threshold. Reset output timing is shown
in Figure 2.
The CAT140xx devices protect mPs against brownout
failure. Short duration V
CC
transients of 4 msec or less and
100 mV amplitude typically do not generate a Reset pulse.
Figure 1 shows the maximum pulse duration of
negative−going V
CC
transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing V
TH
− V
CC
), the maximum
pulse duration decreases. In this test, the V
CC starts from an
initial voltage of 0.5 V above the threshold and drops below
it by the amplitude of the overdrive voltage (V
TH
− V
CC
).
Figure 1. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
TRANSIENT DURATION [μs]
RESET OVERDRIVE V
TH
- V
CC
[mV]
T
AMB
= 25ºC
CAT140xxM
CAT140xxZ
Figure 2. RESET Output Timing
V
CC
PURST
t
PURST
t
RPD
t
RVALID
V
V
TH
RESET
RESET
CAT140xx9
CAT140xx1
RPD
t
CAT140xx
http://onsemi.com
6
EMBEDDED EEPROM OPERATION
The CAT140xx supports the Inter−Integrated Circuit
(I
2
C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT140xx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I
2
C BUS PROTOCOL
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 3). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when following a
Write command) or sends the Slave into standby mode
(when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 4. A
2, A1 and A0 must match the state of the external
address pins, and a
10, a9 and a8 are internal address bits.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9
th clock cycle (Figure 5). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
th
clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 6.
Figure 3. START/STOP Conditions
START
CONDITION
STOP
CONDITION
SDA
SCL
P1-P3P4-P6P7-P9P10-P11

CAT140029TWI-G

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Buy CAT140029TWI-G
Manufacturer:
ON Semiconductor
Description:
Supervisory Circuits w/2k I2C
Lifecycle:
New from this manufacturer.
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