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CAT140029TWI-G

P1-P3P4-P6P7-P9P10-P11
CAT140xx
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7
Figure 4. Slave Address Bits
a
10
a
9
a
8
R/W CAT14016
A
2
a
9
a
8
R/W CAT14008
A
2
A
1
a
8
R/W CAT14004
1A
2
A
1
A
0
R/W CAT1400201 0
1010
1010
1010
Figure 5. Acknowledge Timing
1
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROMTRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK DELAY (≤ t
AA
)
ACK SETUP (≥ t
SU:DAT
)
89
Figure 6. Bus Timing
t
HIGH
SCL
SDA IN
SDA OUT
t
LOW
t
F
t
LOW
t
R
t
BUF
t
SU:STO
t
SU:DAT
t
HD:DAT
t
HD:STA
t
SU:STA
t
AA
t
DH
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAT140xx. After receiving another
acknowledge from the Slave, the Master transmits the data
byte to be written into the addressed memory location. The
CAT140xx device will acknowledge the data byte and the
Master generates the STOP condition, at which time the
device begins its internal Write cycle to nonvolatile memory
(Figure 7). While this internal cycle is in progress (t
WR
), the
SDA output will be tristated and the CAT140xx will not
respond to any request from the Master device (Figure 8).
Page Write
The CAT140xx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 9). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
CAT140xx
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8
transmitted the CAT140xx will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAT140xx in a single
write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT140xx initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT140xx is still busy
with the write operation, NoACK will be returned. If the
CAT140xx has completed the internal write operation, an
ACK will be returned and the host can then proceed with the
next read or write operation.
Figure 7. Byte Write Sequence
ADDRESS
BYTE
DATA
BYTE
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
a
7⎟
a
0
d
7÷
d
0
Figure 8. Write Cycle Timing
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK8
th
Bit
Byte n
SCL
SDA
Figure 9. Page Write Timing
A
C
K
A
C
K
A
C
K
S
T
O
P
S
A
C
K
A
C
K
S
T
A
R
T
P
SLAVE
ADDRESS
n = 1
P ≤
15
ADDRESS
BYTE
n n+1 n+P
ACTIVITY:
MASTER
SLAVE
BUS
DATA
BYTE
DATA
BYTE
DATA
BYTE
CAT140xx
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9
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT140xx will interpret this as a request for data
residing at the current byte address in memory. The
CAT140xx will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT140xx
returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
address of the location it wishes to read. After the CAT140xx
acknowledges the byte address, the Master device resends
the START condition and the slave address, this time with
the R/W bit set to one. The CAT140xx then responds with
its acknowledge and sends the requested data byte. The
Master device does not acknowledge the data (NoACK) but
will generate a STOP condition (Figure 11).
Sequential Read
If during a Read session, the Master acknowledges the 1
st
data byte, then the CAT140xx will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap−around at end of memory (rather than end of page).
POWER−ON RESET (POR)
Each CAT140xx incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
A CAT140xx device will power up into Standby mode
after V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi−directional POR feature protects the
device against ‘brown−out’ failure following a temporary
loss of power.
Delivery State
The CAT140xx is shipped erased, i.e., all bytes are FFh.
Figure 10. Immediate Read Sequence and Timing
SCL
SDA8
th
Bit
STOPNO ACKDATA OUT
8
SLAVE
ADDRESS
S
A
C
K
DATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
9
P1-P3P4-P6P7-P9P10-P11

CAT140029TWI-G

Mfr. #:
Buy CAT140029TWI-G
Manufacturer:
ON Semiconductor
Description:
Supervisory Circuits w/2k I2C
Lifecycle:
New from this manufacturer.
Delivery:
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