AT45DB041A
13
Reset Timing (Inactive Clock Polarity Low Shown)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (except Status Register Read)
Notes: 1. r designates bits reserved for larger densities.
2. It is recommended that r be a logical 0 for densities of 4M bits or smaller.
3. For densities larger than 4M bits, the r bits become the most significant Page Address bit for the appropriate density.
CS
SCK
RESET
SO
HIGH IMPEDANCE HIGH IMPEDANCE
SI
tRST
tREC tCSS
SI CMD 8 bits
8 bits
8 bits
MSB
Reserved for
larger densities
Page Address
(PA10-PA0)
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
LSBr r r r X X X X X X X X X X X X X X X X X X X X
AT45DB041A
14
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
Main Memory Page Program through Buffers
Buffer Write
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)
I/O INTERFACE
SI
BUFFER 1 TO
MAIN MEMORY
PAGE PROGRAM
MAIN MEMORY
PAGE PROGRAM
THROUGH BUFFER 2
BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM
MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER 1
BUFFER 1
WRITE
BUFFER 2
WRITE
SI
CMD n n+1 Last Byte
· Completes writing into selected buffer
· Starts self-timed erase/program operation
CS
r r r r, PA10-7 PA6-0, BFA8 BFA7-0
SI
CMD X
X···X, BFA8
BFA7-0
n
n+1
Last Byte
· Completes writing into selected buffer
CS
SI
CMD r r r r, PA10-7 PA6-0, X
CS
Starts self-timed erase/program operation
X
Each transition represents
8 bits and 8 clock c
y
cles
n = 1st byte read
n+1 = 2nd byte read
AT45DB041A
15
Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
Main Memory Page Read
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Buffer Read
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)
I/O INTERFACE
MAIN MEMORY
PAGE TO
BUFFER 1
MAIN MEMORY
PAGE TO
BUFFER 2
MAIN MEMORY
PAGE READ
BUFFER 1
READ
BUFFER 2
READ
SO
SI
CMD
r r r r, PA10-7
PA6-0, BA8
BA7-0 X
XXX
CS
n n+1
SO
SI
CMD
r r r r, PA10-7 PA6-0, X X
Starts reading page data into buffer
CS
SO
SI
CMD
X
X···X, BFA8
BFA7-0
CS
n n+1
SO
X
Each transition represents
8 bits and 8 clock c
y
cles
n = 1st byte read
n+1 = 2nd byte read

AT45DB041A-RC-2.5

Mfr. #:
Manufacturer:
Description:
IC FLASH 4M SPI 10MHZ 28SOIC
Lifecycle:
New from this manufacturer.
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