.....................Document #: 38-07094 Rev. *B Page 17 of 20
PCI Clock Outputs, PCI (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
t
P
Period Measured on the rising edge at 1.5V 30 ns
t
H
High Time Duration of clock cycle above 2.4V 12 ns
t
L
Low Time Duration of clock cycle below 0.4V 12 ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns
t
D
Duty Cycle Measured on the rising and falling edges at 1.5V 45 55 %
t
JC
Jitter, Cycle-to-Cycle Measured on the rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
250 ps
t
SK
Output Skew Measured on the rising edge at 1.5V 500 ps
t
O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on the rising
edge at 1.5V. CPU leads PCI output.
1.5 4 ns
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3ms
Z
o
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
30
REF Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns
t
D
Duty Cycle Measured on the rising and falling edges at 1.5V 45 55 %
f
ST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Z
o
AC Output Impedance Average value during switching transition. Used
for determining series termination value.
40
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz
f
D
Deviation from 48 MHz (48.008 – 48)/48 +167 ppm
m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns
t
D
Duty Cycle Measured on the rising and falling edges at 1.5V 45 55 %
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Z
o
AC Output Impedance Average value during switching transition. Used
for determining series termination value.
40
