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CY28317PVXC-2T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
CY28317-2
.......................Document #: 38-07094 Rev. *B Page 7 of 20
Bit 5 27 48MHz 1 (Active/Inactive)
Bit 4 26 24_48MHz 1 (Active/Inactive)
Bit 3 – Reserved 1 Reserved
Bit 2 31, 30 SDRAM4:5 1 (Active/Inactive)
Bit 1 34, 33 SDRAM2:3 1 (Active/Inactive)
Bit 0 37, 36 SDRAM0:1 1 (Active/Inactive)
Byte 4: Control Register 4
Bit Pin# Name Default Description
Bit 7 – Reserved 0 Reserved
Bit 6 – Reserved 0 Reserved
Bit 5 – Reserved 0 Reserved
Bit 4 – Reserved 0 Reserved
Bit 3 – Reserved 0 Reserved
Bit 2 – Reserved 0 Reserved
Bit 1 – Reserved 0 Reserved
Bit 0 – Reserved 0 Reserved
Byte 3: Control Register 3
Bit Pin# Name Default Description
Byte 5: Control Register 5
Bit Pin# Name Default Description
Bit 7 – Reserved 0 Reserved
Bit 6 – Reserved 0 Reserved
Bit 5 – Reserved 0 Reserved
Bit 4 – CPU1
Stop Control
0 0 = CPU1 will be stopped when
CPU_STOP# is active
1 = CPU1 will NOT be stopped when
CPU_STOP# is active
Bit 3 – CPU0
Stop Control
0 0 = CPU0 will be stopped when CPU_STOP# is active
1 = CPU0 will NOT be stopped when CPU_STOP# is
active
Bit 2 – CPUT and CPUC
Stop
Control
0 0 = CPUT and CPUC will be stopped when
CPU_STOP# is active
1 = CPUT and CPUC will NOT be stopped when
CPU_STOP# is active
Bit 1 2 REF1 1 (Active/Inactive)
Bit 0 3 REF0 1 (Active/Inactive)
Byte 6: Watchdog Timer Register
Bit Name Default Pin Description
Bit 7 PCI_Skew1 0 PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
Bit 6 PCI_Skew0 0
CY28317-2
.......................Document #: 38-07094 Rev. *B Page 8 of 20
Bit 5 WD_TIMER4 1 These bits store the time-out value of the Watchdog Timer. The scale of the
timer is determined by the prescaler.
The timer can support a value of 150 ms to 4.8 sec when the prescaler is set
to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec
to 80 sec.
When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and
generate Reset if RST_EN_WD is enabled.
Bit 4 WD_TIMER3 1
Bit 3 WD_TIMER2 1
Bit 2 WD_TIMER1 1
Bit 1 WD_TIMER0 1
Bit 0 WD_PRE_SC
ALER
0 0 = 150 ms
1 = 2.5 sec
Byte 6: Watchdog Timer Register (continued)
Bit Name Default Pin Description
Byte 7: Control Register 7
Bit Pin# Name Default Pin Description
Bit 7 – Reserved 0 Reserved
Bit 6 25 24_48MHz_DRV 1 0 = Norm, 1 = High Drive
Bit 5 26 48MHz_DRV 1 0 = Norm, 1 = High Drive
Bit 4 – Reserved 0 Reserved
Bit 3 – Reserved 0 Reserved
Bit 2 – Reserved 0 Reserved
Bit 1 – Reserved 0 Reserved
Bit 0 – Reserved 0 Reserved
Byte 8: Vendor ID and Revision ID Register (Read Only)
Bit Name Default Pin Description
Bit 7 Revision_ID3 0 Revision ID bit[3]
Bit 6 Revision_ID2 0 Revision ID bit[2]
Bit 5 Revision_ID1 0 Revision ID bit[1]
Bit 4 Revision_ID0 0 Revision ID bit[0]
Bit 3 Vendor_ID3 1 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read-only.
Bit 2 Vendor_ID2 0 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read-only.
Bit 1 Vendor _ID1 0 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read-only.
Bit 0 Vendor _ID0 0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read-only.
Byte 9: System RESET and Watchdog Timer Register
Bit Name Default Pin Description
Bit 7 SDRAM_DRV 0 SDRAM clock output drive strength
0 = Normal
1 = High Drive
Bit 6 PCI_DRV 0 PCI clock output drive strength
0 = Normal
1 = High Drive
Bit 5 Reserved 0 Reserved
Bit 4 RST_EN_WD 0 This bit will enable the generation of a Reset pulse when a Watchdog Timer
time-out occurs.
0 = Disabled
1 = Enabled
CY28317-2
.......................Document #: 38-07094 Rev. *B Page 9 of 20
Bit 3 RST_EN_FC 0 This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Bit 2 WD_TO_STATUS 0 Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write)
Bit 1 WD_EN 0 0 = Stop and reload Watchdog Timer. Unlock CY28317-2 from recovery
frequency mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency change
occurs.
Note: CY28317-2 will generate a system reset, reload a recovery frequency,
and lock itself into a recovery frequency mode after a Watchdog Timer time-out
occurs. Under recovery frequency mode, CY28317-2 will not respond to any
attempt to change output frequency via the SMBus control bytes. System
software can unlock CY28317-2 from its recovery frequency mode by clearing
the WD_EN bit.
Bit 0 CPU0:1_DRV 0 CPU0:1 clock output drive strength
0 = Normal
1 = High Drive
Byte 9: System RESET and Watchdog Timer Register (continued)
Bit Name Default Pin Description
Byte 10: Skew Control Register
Bit Name Default Description
Bit 7 CPU0:1_Skew2 0 CPU 0:1 output skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 6 CPU0:1_Skew1 0
Bit 5 CPU0:1_Skew0 0
Bit 4 Reserved 0 Reserved
Bit 3 Reserved 0 Reserved
Bit 2 Reserved 0 Reserved
Bit 1 CPUT&C_Skew1 0 CPUT and CPUC output skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Bit 0 CPUT&C_Skew0 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

CY28317PVXC-2T

Mfr. #:
Buy CY28317PVXC-2T
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products NB clk for VIATM SDRAM chipsets / Tualatin
Lifecycle:
New from this manufacturer.
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