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CY28317PVXC-2T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
CY28317-2
.......................Document #: 38-07094 Rev. *B Page 4 of 20
Serial Data Interface
The CY28317-2 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol supports byte/word Write,
byte/word Read, block Write and block Read operations from
the controller. For block Write/Read operations, the bytes must
be accessed in sequential order from lowest to highest byte
with the ability to stop after any complete byte has been trans-
ferred. For byte/word Write and byte Read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code.
The definition for the command code is defined as shown in
Table 2.
Table 2. Command Code Definition
Bit Descriptions
7 0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
6:0 Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
Table 3. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1Start 1Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code – 8 bits
‘00000000’ stands for block operation
11:18 Command Code – 8 bits
‘00000000’ stands for block operation
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte count – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29:36 Data byte 0 – 8 bits 28 Read
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 1 – 8 bits 30:37 Byte count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge
... Data byte N/Slave acknowledge... 39:46 Data byte from slave – 8 bits
... Data byte N – 8 bits 47 Acknowledge
... Acknowledge from slave 48:55 Data byte from slave – 8 bits
... Stop 56 Acknowledge
... Data bytes from slave/Acknowledge
... Data byte N from slave - 8 bits
... Not acknowledge
... Stop
CY28317-2
.......................Document #: 38-07094 Rev. *B Page 5 of 20
Table 4. Word Read and Word Write Protocol
Word Write Protocol Word Read Protocol
Bit Description Bit Description
1Start 1Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
11:18 Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Data byte low – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29:36 Data byte high – 8 bits 28 Read
37 Acknowledge from slave 29 Acknowledge from slave
38 Stop 30:37 Data byte low from slave – 8 bits
38 Acknowledge
39:46 Data byte high from slave – 8 bits
47 Not acknowledge
48 Stop
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
11:18 Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Data byte – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29 Stop 28 Read
29 Acknowledge from slave
30:37 Data byte from slave – 8 bits
38 Not acknowledge
39 Stop
CY28317-2
.......................Document #: 38-07094 Rev. *B Page 6 of 20
CY28317-2 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Write with 1" must be written to one
during initialization.
Byte 0: Control Register 0
Bit Pin# Name Default Description
Bit 7 – Spread Select1 0 See definition in Bit[0]
Bit 6 – SEL2 0 See Table 6
Bit 5 – SEL1 0 See Table 6
Bit 4 – SEL0 0 See Table 6
Bit 3 – FS_Override 0 0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
Bit 2 – SEL4 0 See Table 6
Bit 1 – SEL3 0 See Table 6
Bit 0 – Spread Select0 0 ‘00’ = OFF
‘01’ = –0.5%
‘10’ = ±0.5%
‘11’ = ±0.25%
Byte 1: Control Register 1
Bit Pin# Name Default Description
Bit 7 10 Latched FS4 input X Latched FS[4:0] inputs. These bits are read-only.
Bit 6 11 Latched FS3 input X
Bit 5 2 Latched FS2 input X
Bit 4 26 Latched FS1 input X
Bit 3 27 Latched FS0 input X
Bit 2 48 CPU0 1 (Active/Inactive)
Bit 1 47 CPU1 1 (Active/Inactive)
Bit 0 44, 43 CPUT, CPUC 1 (Active/Inactive)
Byte 2: Control Register 2
Bit Pin# Name Default Description
Bit 7 39 SDRAM6 1 (Active/Inactive)
Bit 6 10 PCI0_F 1 (Active/Inactive)
Bit 5 17 PCI6 1 (Active/Inactive)
Bit 4 16 PCI5 1 (Active/Inactive)
Bit 3 15 PCI4 1 (Active/Inactive)
Bit 2 14 PCI3 1 (Active/Inactive)
Bit 1 13 PCI2 1 (Active/Inactive)
Bit 0 11 PCI1 1 (Active/Inactive)
Byte 3: Control Register 3
Bit Pin# Name Default Description
Bit 7 – Reserved 1 Reserved
Bit 6 – SEL_48MHz 0 0 = 24 MHz
1 = 48 MHz
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

CY28317PVXC-2T

Mfr. #:
Buy CY28317PVXC-2T
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products NB clk for VIATM SDRAM chipsets / Tualatin
Lifecycle:
New from this manufacturer.
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