MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
12 ______________________________________________________________________________________
Pin Description
NAME FUNCTION
1, 2, 16–19,
24, 25
16–19
1, 2, 16–19,
24, 25, 31,
34
16–19, 31,
34
D.C. Do Not Connect. Do not connect to this pin.
3333EOC
Active-Low End-of-Conversion Output. Data is valid after the
falling edge of EOC.
4444DV
DD
Digital Positive Power Input. Bypass DV
DD
to DGND with a
0.1µF capacitor.
5 5 5 5 DGND Digital Ground. Connect DGND to AGND.
6 6 6 6 DOUT
Serial Data Output. Data is clocked out on the falling edge of
the SCLK clock in clock modes 00, 01, and 10. Data is
clocked out on the rising edge of the SCLK clock in clock
mode 11. High impedance when CS is high.
7 7 7 7 SCLK
Serial Clock Input. Clocks data in and out of the serial
interface. (Duty cycle must be 40% to 60%.) See Table 4 for
details on programming the clock mode.
8888DIN
Serial Data Input. DIN data is latched into the serial interface
on the falling edge of SCLK.
9–12 9–12 9–12 9–12
OUT0–
OUT3
DAC Outputs
13 13 13 13 AV
DD
Positive Analog Power Input. Bypass AV
DD
to AGND with a
0.1µF capacitor.
14 14 14 14 AGND Analog Ground
15, 23, 32,
33
15, 23, 32,
33
15, 23, 32,
33
15, 23, 32,
33
N.C. No Connection. Not internally connected.
20 20 20 20 LDAC
Active-Low Load DAC. LDAC is an asynchronous active-low
input that updates the DAC outputs. Drive LDAC low to make
the DAC registers transparent.
21 21 21 21 CS
Active-Low Chip-Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance.
22 22 22 22
Reset Select. Selects DAC wake-up mode. Set RES_SEL low
to wake up the DAC outputs with a 100kΩ resistor to GND or
set RES_SEL high to wake up the DAC outputs with a 100kΩ
resistor to V
REF
. Set RES_SEL high to power up the DAC input
register to FFFh. Set RES_SEL low to power up the DAC input
register to 000h.
