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MAX1340BETX+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC
DC ACCURACY (Note 10)
Resolution 12 Bits
Integral Nonlinearity INL ±0.5 ±4 LSB
Differential Nonlinearity DNL Guaranteed monotonic ±1.0 LSB
Offset Error V
OS
(Note 8) ±3 ±10 mV
Offset-Error Drift ±10
ppm of
FS/°C
Gain Error GE (Note 8) ±5 ±10 LSB
Gain Temperature Coefficient ±8
ppm of
FS/°C
DAC OUTPUT
No load 0.02
AV
DD
-
0.02
Output-Voltage Range
10kΩ load to either rail 0.1
AV
DD
-
0.1
V
DC Output Impedance 0.5 Ω
Capacitive Load (Note 11) 1 nF
Resistive Load to AGND R
L
AV
DD
= 4.75V, V
REF
= 4.096V, gain error
< 2%
500 Ω
From power-down mode, AV
DD
= 5V 25
Wake-Up Time (Note 12)
From power-down mode, AV
DD
= 2.7V 21
µs
1kΩ Output Termination Programmed in power-down mode 1 kΩ
100kΩ Output Termination
At wake-up or programmed in
power-down mode
100 kΩ
DYNAMIC PERFORMANCE (Notes 5, 13)
Output-Voltage Slew Rate SR Positive and negative 3 V/µs
Output-Voltage Settling Time t
S
To 1 LSB, 400 - C00 hex (Note 7) 2 5 µs
Digital Feedthrough Code 0, all digital inputs from 0 to DV
DD
0.5 nV•s
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048 4 nV
•s
From V
REF
660
Output Noise (0.1Hz to 50MHz)
Using internal reference 720
µV
P-P
From V
REF
260
Output Noise (0.1Hz to 500kHz)
Using internal reference 320
µV
P-P
DAC-to-DAC Transition
Crosstalk
0.5 nV
•s
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= 4.75V to 5.25V, external reference V
REF
= 4.096V, f
CLK
= 3.6MHz (50% duty cycle), T
A
= -40°C to +85°C, unless
otherwise noted. Typical values are at AV
DD
= DV
DD
= 5V, T
A
= +25°C. Outputs are unloaded, unless otherwise noted.)
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERNAL REFERENCE
REF1 Output Voltage 4.066 4.096 4.126 V
REF1 Temperature Coefficient TC
REF
±30
ppm/°C
REF1 Short-Circuit Current V
REF
= 4.096V 0.63 mA
EXTERNAL-REFERENCE INPUT
REF1 Input-Voltage Range V
REF1
REF modes 01, 10, and 11 (Note 4) 0.7 AV
DD
V
REF1 Input Impedance R
REF1
70 100 130 kΩ
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)
Input-Voltage High V
IH
DV
DD
= 2.7V to 5.25V 2.4 V
DV
DD
= 3.6V to 5.25V 0.8
Input-Voltage Low V
IL
DV
DD
= 2.7V to 3.6V 0.6
V
Input Leakage Current I
L
±0.01 ±10 µA
Input Capacitance C
IN
15 pF
DIGITAL OUTPUT (DOUT) (Note 14)
Output-Voltage Low V
OL
I
SINK
= 2mA 0.4 V
Output-Voltage High V
OH
I
SOURCE
= 2mA
DV
DD
-
0.5
V
Tri-State Leakage Current ±10 µA
Tri-State Output Capacitance C
OUT
15 pF
DIGITAL OUTPUT (EOC) (Note 14)
Output-Voltage Low V
OL
I
SINK
= 2mA 0.4 V
Output-Voltage High V
OH
I
SOURCE
= 2mA
DV
DD
-
0.5
V
Tri-State Leakage Current ±10 µA
Tri-State Output Capacitance C
OUT
15 pF
DIGITAL OUTPUTS (GPIO_) (Note 14)
I
SINK
= 2mA 0.4
GPIOC_ Output-Voltage Low
I
SINK
= 4mA 0.8
V
GPIOC_ Output-Voltage High I
SOURCE
= 2mA
DV
DD
-
0.5
V
GPIOA_ Output-Voltage Low I
SINK
= 15mA 0.8 V
GPIOA_ Output-Voltage High I
SOURCE
= 15mA
DV
DD
-
0.8
V
Tri-State Leakage Current ±10 µA
Tri-State Output Capacitance C
OUT
15 pF
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= 4.75V to 5.25V, external reference V
REF
= 4.096V, f
CLK
= 3.6MHz (50% duty cycle), T
A
= -40°C to +85°C, unless
otherwise noted. Typical values are at AV
DD
= DV
DD
= 5V, T
A
= +25°C. Outputs are unloaded, unless otherwise noted.)
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
6 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage DV
DD
4.75 AV
DD
V
Idle, all blocks shut down 0.2 4 µA
Digital Positive-Supply Current DI
DD
Only ADC on, external reference 1 mA
Analog Positive-Supply Voltage AV
DD
4.75 5.25 V
Idle, all blocks shut down 0.2 2 µA
f
SAMPLE
= 225ksps 2.8 4.2
Only ADC on,
external reference
f
SAMPLE
= 100ksps 2.6
Analog Positive-Supply Current A
IDD
All DACs on, no load, internal reference 1.5 4.0
mA
REF1 Positive-Supply Rejection PSRR AV
DD
= 4.75V -80 dB
DAC Positive-Supply Rejection PSRD
Output code = FFFhex, AV
DD
= 4.75V to
5.25V
±0.1 ±0.5 mV
ADC Positive-Supply Rejection PSRA Full-scale input, AV
DD
= 4.75V to 5.25V ±0.06 ±0.5 mV
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period t
CP
40 ns
SCLK Pulse-Width High t
CH
40/60 duty cycle 16 ns
SCLK Pulse-Width Low t
CL
60/40 duty cycle 16 ns
GPIO Output Rise/Fall After
CS Rise
t
GOD
C
LOAD
= 20pF 100 ns
GPIO Input Setup Before CS Fall t
GSU
0ns
LDAC Pulse Width t
LDACPWL
20 ns
C
LOAD
= 20pF, SLOW = 0 1.8 12.0
SCLK Fall to DOUT Transition
(Note 16)
t
DOT
C
LOAD
= 20pF, SLOW = 1 10 40
ns
C
LOAD
= 20pF, SLOW = 0 1.8 12.0
SCLK Rise to DOUT Transition
(Notes 16, 17)
t
DOT
C
LOAD
= 20pF, SLOW = 1 10 40
ns
CS Fall to SCLK Fall Setup Time t
CSS
10 ns
S C LK Fal l to CS Ri se S etup Ti m et
CSH
0 2000 ns
DIN to SCLK Fall Setup Time t
DS
10 ns
DIN to SCLK Fall Hold Time t
DH
0ns
CS Pulse-Width High t
CSPWH
50 ns
CS Rise to DOUT Disable t
DOD
C
LOAD
= 20pF 25 ns
CS Fall to DOUT Enable t
DOE
C
LOAD
= 20pF 1.5 25.0 ns
EOC Fall to CS Fall t
RDS
30 ns
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= 4.75V to 5.25V, external reference V
REF
= 4.096V, f
CLK
= 3.6MHz (50% duty cycle), T
A
= -40°C to +85°C, unless
otherwise noted. Typical values are at AV
DD
= DV
DD
= 5V, T
A
= +25°C. Outputs are unloaded, unless otherwise noted.)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

MAX1340BETX+

Mfr. #:
Buy MAX1340BETX+
Manufacturer:
Maxim Integrated
Description:
Data Acquisition ADCs/DACs - Specialized 12-Bit 8Ch 300ksps 5.25 Precision ADC
Lifecycle:
New from this manufacturer.
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