MAX1340BETX+ Datasheet MAX1342BETX+, MAX1346BETX+, MAX1340BETX+ | P16-P18

MAX1340/MAX1342/MAX1346/MAX1348

12-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

16 ______________________________________________________________________________________

Table 1. Command Byte (MSB First)

Conversion* 1 X CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 TEMP

Setup 0 1 CKSEL1 CKSEL0 REFSEL1 REFSEL0 DIFFSEL1 DIFFSEL0

ADC Averaging 0 0 1 AVGON NAVG1 NAVG0 NSCAN1 NSCAN0

DAC Select 0 0 0 1 XXXX

Reset 0 0 0 0 1 RESET SLOW FBGON

GPIO Configure** 0 0 000011

GPIO Write** 0 0 000010

GPIO Read** 0 0 000001

No Operation 0 0 000000

X = Don’t care.

CHESL2 bit is only valid on the MAX1340/MAX1342. Set CHSEL2 to zero on the MAX1346/MAX1348.

Only applicable on the MAX1342/MAX1348.

Power-Up Default State

The MAX1340/MAX1342/MAX1346/MAX1348 power up

with all blocks in shutdown (including the reference). All

registers power up in state 00000000, except for the

setup register and the DAC input register. The setup

REFSEL1 = 1. The DAC input register powers up to

FFFh when RES_SEL is high and powers up to 000h

when RES_SEL is low.

12-Bit ADC

The MAX1340/MAX1342/MAX1346/MAX1348 ADCs use

a fully differential successive-approximation register

(SAR) conversion technique and on-chip track-and-

hold (T/H) circuitry to convert temperature and voltage

signals into 12-bit digital results. The analog inputs

accept both single-ended and differential input signals.

Single-ended signals are converted using a unipolar

transfer function, and differential signals are converted

using a selectable bipolar or unipolar transfer function.

See the

ADC Transfer Functions

section for more data.

ADC Clock Modes

When addressing the setup, register bits 5 and 4 of the

command byte (CKSEL1 and CKSEL0, respectively)

control the ADC clock modes. See Table 5. Choose

between four different clock modes for various ways to

start a conversion and determine whether the acquisi-

tions are internally or externally timed. Select clock

mode 00 to configure CNVST/AIN_ to act as a conver-

sion start and use it to request internally timed conver-

sions, without tying up the serial bus. In clock mode 01,

use CNVST to request conversions one channel at a

time, thereby controlling the sampling speed without

tying up the serial bus. Request and start internally

timed conversions through the serial interface by writ-

ing to the conversion register in the default clock mode,

10. Use clock mode 11 with SCLK up to 3.6MHz for

externally timed acquisitions to achieve sampling rates

up to 225ksps. Clock mode 11 disables scanning and

averaging. See Figures 6–9 for timing specifications on

how to begin a conversion.

These devices feature an active-low, end-of-conversion

output. EOC goes low when the ADC completes the last

requested operation and is waiting for the next com-

mand byte. EOC goes high when CS or CNVST go low.

EOC is always high in clock mode 11.

Single-Ended or Differential Conversions

The MAX1340/MAX1342/MAX1346/MAX1348 use a fully

differential ADC for all conversions. When a pair of

inputs are connected as a differential pair, each input is

connected to the ADC. When configured in single-

ended mode, the positive input is the single-ended

channel and the negative input is referred to AGND.

See Figure 2.

In differential mode, the T/H samples the difference

between two analog inputs, eliminating common-mode

DC offsets and noise. IN+ and IN- are selected from the

following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,

AIN6/AIN7. AIN0–AIN3 are available on all devices.

AIN0–AIN7 are available on the MAX1340/MAX1342.

See Tables 5–8 for more details on configuring the

inputs. For the inputs that are configurable as CNVST,

REF2, and an analog input, only one function can be

used at a time.

Unipolar or Bipolar Conversions

Address the unipolar- and bipolar-mode registers

through the setup register (bits 1 and 0). See Table 5 for

MAX1340/MAX1342/MAX1346/MAX1348

12-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 17

the setup register. See Figures 3 and 4 for the transfer-

function graphs. Program a pair of analog inputs for dif-

ferential operation by writing a one to the appropriate bit

of the bipolar- or unipolar-mode register. Unipolar mode

sets the differential input range from 0 to V

REF1.

A nega-

tive differential analog input in unipolar mode causes the

digital output code to be zero. Selecting bipolar mode

sets the differential input range to ±V

REF1

/2. The digital

output code is binary in unipolar mode and two’s com-

plement in bipolar mode.

In single-ended mode, the MAX1340/MAX1342/

MAX1346/MAX1348 always operate in unipolar mode.

The analog inputs are internally referenced to AGND

with a full-scale input range from 0 to the selected refer-

ence voltage.

Analog Input (T/H)

The equivalent circuit of Figure 2 shows the ADC input

architecture of the MAX1340/MAX1342/MAX1346/

MAX1348. In track mode, a positive input capacitor is

connected to AIN0–AIN7 in single-ended mode and

AIN0, AIN2, AIN4, and AIN6 in differential mode. A neg-

ative input capacitor is connected to AGND in single-

ended mode or AIN1, AIN3, AIN5, and AIN7 in

differential mode. For external T/H timing, use clock

mode 01. After the T/H enters hold mode, the difference

between the sampled positive and negative input volt-

ages is converted. The input capacitance charging rate

determines the time required for the T/H to acquire an

input signal. If the input signal’s source impedance is

high, the required acquisition time lengthens.

Any source impedance below 300Ω does not signifi-

cantly affect the ADC’s AC performance. A high-imped-

ance source can be accommodated either by

lengthening t

ACQ

(only in clock mode 01) or by placing

a 1µF capacitor between the positive and negative ana-

log inputs. The combination of the analog-input source

impedance and the capacitance at the analog input cre-

ates an RC filter that limits the analog input bandwidth.

Input Bandwidth

The ADC’s input-tracking circuitry has a 1MHz small-sig-

nal bandwidth, making it is possible to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. Anti-alias prefiltering

of the input signals is necessary to avoid high-frequency

signals aliasing into the frequency band of interest.

Analog-Input Protection

Internal electrostatic-discharge (ESD) protection diodes

clamp all analog inputs to AV

and AGND, allowing

the inputs to swing from (AGND - 0.3V) to (AV

0.3V) without damage. However, for accurate conver-

sions near full scale, the inputs must not exceed AV

by more than 50mV or be lower than AGND by 50mV. If

an analog input voltage exceeds the supplies, limit the

input current to 2mA.

Internal FIFO

The MAX1340/MAX1342/MAX1346/MAX1348 contain a

first-in/first-out (FIFO) buffer that holds up to 16 ADC

results plus one temperature result. The internal FIFO

allows the ADC to process and store multiple internally

clocked conversions and a temperature measurement

without being serviced by the serial bus.

If the FIFO is filled and further conversions are request-

ed without reading from the FIFO, the oldest ADC

results are overwritten by the new ADC results. Each

result contains 2 bytes, with the MSB preceded by four

leading zeros. After each falling edge of CS, the oldest

available pair of bytes of data is available at DOUT,

MSB first. When the FIFO is empty, DOUT is zero.

The first 2 bytes of data read out after a temperature

measurement always contain the 12-bit temperature

result, preceded by four leading zeros, MSB first. If

another temperature measurement is performed before

the first temperature result is read out, the old measure-

ment is overwritten by the new result. Temperature

results are in degrees Celsius (two’s complement), at a

resolution of 8 LSB per degree. See the

Temperature

Measurements

section for details on converting the dig-

ital code to a temperature.

AIN0–AIN7

(SINGLE-ENDED),

AIN0, AIN2,

AIN4, AIN6

(DIFFERENTIAL)

COMPARATOR

HOLD

ACQ

HOLD

ACQ

HOLD

/ 2

REF1

AGND

CIN+

CIN-

DAC

AGND

(SINGLE-ENDED),

AIN1, AIN3,

AIN5, AIN7

(DIFFERENTIAL)

Figure 2. Equivalent Input Circuit

MAX1340/MAX1342/MAX1346/MAX1348

12-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

18 ______________________________________________________________________________________

12-Bit DAC

In addition to the 12-bit ADC, the MAX1340/MAX1342/

MAX1346/MAX1348 also include four voltage-output,

12-bit, monotonic DACs with less than 4 LSB integral

nonlinearity error and less than 1 LSB differential nonlin-

earity error. Each DAC has a 2µs settling time and ultra-

low glitch energy (4nV•s). The 12-bit DAC code is

unipolar binary with 1 LSB = V

REF

/ 4096.

DAC Digital Interface

Figure 1 shows the functional diagram of the MAX1342.

The shift register converts a serial 16-bit word to parallel

data for each input register operating with a clock rate

up to 25MHz. The SPI-compatible digital interface to the

shift register consists of CS, SCLK, DIN, and DOUT.

Serial data at DIN is loaded on the falling edge of SCLK.

Pull CS low to begin a write sequence. Begin a write to

the DAC by writing 0001XXXX as a command byte. The

last 4 bits of the DAC select register are don’t-care bits.

See Table 10. Write another 2 bytes to the DAC inter-

face register following the command byte to select the

appropriate DAC and the data to be written to it. See

Tables 17 and 18.

The four double-buffered DACs include an input and a

DAC register. The input registers are directly connect-

ed to the shift register and hold the result of the most

recent write operation. The four 12-bit DAC registers

hold the current output code for the respective DAC.

Data can be transferred from the input registers to the

DAC registers by pulling LDAC low or by writing the

appropriate DAC command sequence at DIN. See

Table 17. The outputs of the DACs are buffered through

four rail-to-rail op amps.

The MAX1340/MAX1342/MAX1346/MAX1348 DAC out-

put-voltage range is based on the internal reference or

an external reference. Write to the setup register (see

Table 5) to program the reference. If using an external

voltage reference, bypass REF1 with a 0.1µF capacitor

to AGND. The internal reference is 4.096V. When using

an external reference, the voltage range is 0.7V to AV

DAC Transfer Function

See Table 2 for various analog outputs from the DAC.

DAC Power-On Wake-Up Modes

The state of the RES_SEL input determines the wake-up

state of the DAC outputs. Connect RES_SEL to AV

AGND upon power-up to be sure the DAC outputs

wake up to a known state. Connect RES_SEL to AGND

to wake up all DAC outputs at 000h. While RES_SEL is

low, the 100kΩ internal resistor pulls the DAC outputs to

AGND and the output buffers are powered down.

Connect RES_SEL to AV

to wake up all DAC outputs

at FFFh. While RES_SEL is high, the 100kΩ pullup

resistor pulls the DAC outputs to V

REF1

and the output

buffers are powered down.

DAC Power-Up Modes

See Table 18 for a description of the DAC power-up

and power-down modes.

GPIOs

In addition to the internal ADC and DAC, the

MAX1342/MAX1348 also provide four GPIO channels,

GPIOA0, GPIOA1, GPIOC0, GPIOC1. Read and write to

the GPIOs as detailed in Table 1 and Tables 12–16. Also,

see the

GPIO Command

section. See Figures 11 and 12

for GPIO timing.

Write to the GPIOs by writing a command byte to the

GPIO command register. Write a single data byte to the

MAX1342/MAX1348 following the command byte.

DAC CONTENTS

MSB LSB

ANALOG OUTPUT

1111 1111 1111

1000 0000 0001

1000 0000 0000

0111 0111 0111

0000 0000 0001

0000 0000 0000 0

⎛

⎝

⎜

⎞

⎠

⎟

REF

4095

4096

⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

REF

2048

4096 2

⎛

⎝

⎜

⎞

⎠

⎟

REF

2047

4096

⎛

⎝

⎜

⎞

⎠

⎟

REF

4096

⎛

⎝

⎜

⎞

⎠

⎟

REF

2049

4096

Table 2. DAC Output Code Table

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39

MAX1340BETX+

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Data Acquisition ADCs/DACs - Specialized 12-Bit 8Ch 300ksps 5.25 Precision ADC

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