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IDTCV115-2PVG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
COMMERCIAL TEMPERATURE RANGE
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
1
APRIL 2004
IDTCV115-2
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC™
CLOCK FOR P4 PROCESSOR
SATA PLL
SCC
SATA/
CPU[1:0]
SRC[6:5] [3:1]
USB48
DOT96
PCI[4:0], PCIF[2:0]
SRC4 - SATA
PCI/
PCIE/
Host/
48MHz/
96MHz/
MUX
PCIEX PLL
SCC
N Programming
CPU PLL
SCC
N Programming
Fixed PLL
No SCC
14.318MHz
Osc
CPU_ITP/
SRC7
RESET
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2004 Integrated Device Technology, Inc. DSC 6544/9
FEATURES:
• One high precision N Programming PLL for CPU
• One high precision N Programming PLL for SRC/PCI
• One high precision PLL for SATA
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support multiple spread spectrum modulation, down and
center
• Support SMBus block read/write, index read/write
• Selectable output strength for REF, PCI, and 48MHz
• Available in SSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
IDTCV115-2 is a 56 pin clock device, complying the latest Intel CK410
requirements, for Intel advance P4 processors. The CPU output buffer is
designed to support up to 400MHz processor. One dedicated PLL for Serial
ATA clock provides high accuracy frequency. This device also implements
Band-gap referenced IREF to reduce the impact of VDD variation on differential
outputs, which can provide more robust system performance.
Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection,
which allows for isolated changes instead of affecting other clock groups.
KEY SPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• SATA CLK cycle to cycle jitter < 85ps
• Static PLL frequency divide error < 114 ppm
• Static PLL frequency divide error for 48MHz < 5 ppm
OUTPUT TABLE
CPU CPU_ITP/SRC SRC SATA PCI/PCIF REF/PCI REF DOT96 24_48MHz RESET TURBO
2 1 51811 1 1 1 2
COMMERCIAL TEMPERATURE RANGE
2
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
PIN CONFIGURATION
SSOP
TOP VIEW
HW FREQUENCY SELECTION TABLE
FSC, B, A CPU SRC4_SATA SRC[3:1], SCR[7:5] PCI USB DOT REF
101 100 100 100 33.3 48 96 14.318
001 133 100 100 33.3 48 96 14.318
011 166 100 100 33.3 48 96 14.318
010 200 100 100 33.3 48 96 14.318
000 266 100 100 33.3 48 96 14.318
100 333 100 100 33.3 48 96 14.318
110 400 100 100 33.3 48 96 14.318
111 Reserve 100 100 33.3 48 96 14.318
TEST MODE SELECT
(1)
If TEST_SEL sampled above 2V at VTT_PWRGD active LOW
Pin38
(test_mode) CPU SRC PCI/F REF DOT96 USB
1 REF/N REF/N REF/N REF REF/N REF/N
0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between
the Hi-Z and REF/N,
ITP_EN pin 35 pin 36
1 CPUC2_ITP CPUT_ITP
0 SRCC7 SRCT7
ITP_EN
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI1
PCI0
FS_A(REF1/PCI5)
FS_C/REF0
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SCL
SDA
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
Reset#
CPU2_ITP/SRCT7
CPU2_ITP/SRCC7
VDD_SRC
SRCC6
SRCT5
SRCC5
VSS_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD_PCI
V
SS_PCI
PCI2
PCI3
PCI4/Turbo1
VSS_PCI
V
DD_PCI
PCIF0/ITP_EN
PCIF1
VTT_PWRGD/PWRDWN#
VDD_48
FS_B/USB48MHz
VSS_48
DOT_96
DOT_96#
PCIF2
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
VDD_SRC
SRCT6
VSS
VSS_GND
SRCC4_SATA
VDD_suspend
V
SS_CPU
Turbo2
(1)
(2)
(4)
(2)
(2)
(3)
NOTES:
1. After power on, pin 5 is tristate (see Byte 30 and Byte 2).
2. ~ 130KΩ internal pull-up.
3. After power on, REF1/PCI5 is tristate (see Byte 1).
4. Disabled at power on.
COMMERCIAL TEMPERATURE RANGE
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
3
PIN DESCRIPTION
Pin Number Name Type Description
1VDD_PCI PWR 3.3V
2VSS_PCI GND GND
3 PCI2 OUT PCI clock
4 PCI3 OUT PCI clock
5 PCI4/Turbo1 OUT PCI clock output or Turbo input. Byte 30, bit 3 mode selection. Byte 30, bit 3 = 1, PCI clock. 0 = Turbo
mode. In Turbo mode, 1 = load TCN and TPN into CPU and SRC PLL.
6VSS_PCI GND GND
7VDD_PCI PWR 3.3V
8 PCIF0/ITP_EN I/0 PCI clock, free running. CPU_2 select (sampled at VTT_PWRGD assertion), HIGH = CPU_2.
9 PCIF1 OUT PCI clock,
10 PCIF2 OUT PCI clock,
11 VDD_48 PWR 3.3V
12 FS_B/USB48 I/O CPU Frequency selection. 48MHz afterward.
13 VSS_48 GND GND
14 DOT_96T OUT 96MHz 0.7V current mode differential clock output
15 DOT_96C OUT 96MHz 0.7V current mode differential clock output
16 VTT_PWRGD/PWRDWN# I/O 3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and
PCIF_0/ITP_EN inputs. After VTT_PWRGD assertion, active HIGH, becomes a real-time input for
asserting power down (active LOW). Internal pull HIGH.
17 SRCT1 OUT Differential Serial reference clock
18 SRCC1 OUT Differential Serial reference clock
19 VDD_SRC PWR 3.3V
20 VSS GND GND
21 SRCT2 OUT Differential Serial reference clock
22 SRCC2 OUT Differential Serial reference clock
23 SRCT3 OUT Differential Serial reference clock
24 SRCC3 OUT Differential Serial reference clock
25 VSS GND GND
26 SRCT4_SATA OUT SATA clock
27 SRCC4_SATA OUT SATA clock
28 VDD_SRC PWR 3.3V
29 VSS_SRC GND GND
30 SRCC5 OUT Differential Serial reference clock
31 SRCT5 OUT Differential Serial reference clock
32 SRCC6 OUT Differential Serial reference clock
33 SRCT6 OUT Differential Serial reference clock
34 VDD_SRC PWR 3.3V
35 CPUC2_ITP/ SRCC7 OUT Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD assertion = SRC_7
36 CPUT2_ITP/ SRCT7 OUT Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD assertion = SRC_7
37 Turbo2 I N Load TCN2 into CPU PLL. Disabled at power on (see Byte 26).
38 Reset# OUT Reset output
39 IREF OUT Reference current for differential output buffer
40 VSS GND GND
41 CPUC1 OUT Host 0.7V current mode differential clock output
42 CPUT1 OUT Host 0.7V current mode differential clock output
43 V DD_CPU PWR 3.3V
44 CPUC0 OUT Host 0.7V current mode differential clock output
45 CPUT0 OUT Host 0.7V current mode differential clock output
46 SDA I/O SMBus data
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

IDTCV115-2PVG8

Mfr. #:
Buy IDTCV115-2PVG8
Manufacturer:
Description:
IC FLEXPC CLK PROGR P4 56-TSSOP
Lifecycle:
New from this manufacturer.
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