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IDTCV115-2PVG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
COMMERCIAL TEMPERATURE RANGE
4
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
PIN DESCRIPTION (CONT.)
Pin Number Name Type Description
47 SCL IN SMBus CLK
48 VDD_REF PWR 3.3V
49 XTAL_OUT OUT Xtal output
50 XTAL_IN IN Xtal input
51 VSS_REF GND GND
52 FS_C/REF0 I/O CPU frequency selection input at VTT_PWRGD assertion. 14.318 reference clock output afterward.
53 VDD_Suspend POWER Keep supply 3.3V in the power down
54 FS_A(REF1/PCI5) I/O CPU frequency selection input at VTT_PWRGD assertion. 14.318 or PCI reference clock output afterward,
SMBus selectable. Tristate at power on.
55 PCI0 OUT PCI clock
56 PCI1 OUT PCI clock
INDEX BLOCK WRITE PROTOCOL
Bit # of bits From Description
1 1 Master Start
2-9 8 Master D2h
10 1 Slave Ack (Acknowledge)
11-18 8 Master Register offset byte (starting byte)
19 1 Slave Ack (Acknowledge)
20-27 8 Master Byte count, N, (0 is not valid
28 1 Slave Ack (Acknowledge)
29-36 8 Master first data byte (Offset data byte)
37 1 Slave Ack (Acknowledge)
38-45 8 Master 2nd data byte
46 1 Slave Ack (Acknowledge)
:
Master Nth data byte
Slave Acknowledge
Master Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit # of bits From Description
1 1 Master Start
2-9 8 Master D2H
10 1 Slave Ack (Acknowledge)
11-18 8 Master Register offset byte (starting byte)
19 1 Slave Ack (Acknowledge)
20 1 Master Repeated Start
21-28 8 Master D3H
29 1 Slave Ack (Acknowledge)
30-37 8 Slave Byte count, N (block read back of N
bytes), Byte 8
38 1 Master Ack (Acknowledge)
39-46 8 Slave first data byte (Offset data byte)
47 1 Master Ack (Acknowledge)
48-55 8 Slave 2nd data byte
Ack (Acknowledge)
:
Master Ack (Acknowledge)
Slave Nth data byte
Not acknowledge
Master Stop
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
SM PROTOCOL
COMMERCIAL TEMPERATURE RANGE
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
5
CB1_[2:0], CB2_[2:0], CPU MODE
SELECTION
CB[2:0] CPU Mode, MHz
101 100
001 133
011 166
010 200
000 266
100 333
110 400
111 RESERVE
SSC MAGNITUDE CONTROL
SMC[2:0] %
000 OFF
001 - 0.25
010 - 0.5
011 ±0.125
100 ±0.25
101 ±0.375
110 ±0.5
111 ±0.75
PCIS[1:0] PCI
00 33.33
01 36.36
10 40
11
S_CBS[1:0], H_CBS[1:0] BAND
SELECTION
CBS[1:0]
00 FS[C,B,A]
01 CB1_[2:0]
10 CB2_[2:0]
11 Don’t care
PCI
When Byte5 bit6 = 0
S_CNS, S_PNS, H_CNS,H_PNS N
SELECTION
NS[1:0]
00 Standard of Each CPU Mode (Band)
01 N Selection 1
10 N Selection 2
11 Don’t care
N Resolution (MHz) % N =
CPU = 100MHz mode 0.666667 0.67% 150
CPU = 133MHz mode 0.888889 0.67% 150
CPU = 166MHz mode 1.333333 0.8% 125
CPU = 200MHz mode 1.333333 0.67% 150
CPU = 266MHz mode 2.666667 1.00% 100
CPU = 333MHz mode 2.666667 0.8% 125
CPU = 400MHz mode 2.666667 0.67% 150
SRC (PCI Express) 0.666667 0.67% 150
RESOLUTION
S.E. CLOCK STRENGTH SELECTION (PCI, REF, USB48)
Str[1:0] Multiple loads Single loads USB48
00 2L Recommend Recommend
01 1H Recommend
10 1L Recommend
11 2H Recommend Recommend
COMMERCIAL TEMPERATURE RANGE
6
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
BYTE 1
Bit Output(s) Affected Description/Function 0 1 Type Power On Recommended
7 DOT96T, DOT96C Output enable Tristate Enable RW 1
6 Not bonded out Tristate Enable RW 1 0
5 USB48 Output enable Tristate Enable RW 1
4 REF1/PCI5 Mode Select PCI5 REF1 RW 0
3 REF0 Output enable Tristate Enable RW 1
2 CPUT1, CPUC1 Output enable Tristate Enable RW 1
1 CPUT0, CPUC0 Output enable Tristate Enable RW 1
0 REF1/PCI5 Output enable Tristate Enable 0
BYTE 2
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 PCI4 Output enable Tristate Enable RW 1
6 PCI3 Output enable Tristate Enable RW 1
5 PCI2 Output enable Tristate Enable RW 1
4 PCI1 Output enable Tristate Enable RW 1
3 PCI0 Output enable Tristate Enable RW 1
2 PCIF2 Output enable Tristate Enable RW 1
1 PCIF1 Output enable Tristate Enable RW 1
0 PCIF0 Output enable Tristate Enable RW 1
BYTE 3
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 FSC latched value on power up R
6 FSB latched value on power up R
5 FSA latched value on power up R
4 SRCT[7:1] SRCT Pwrdwn drive mode Driven in power down Tristate in power down RW 0
3 CPUT2 CPUT2 Pwrdwn drive mode Driven in power down Tristate in power down RW 0
2 CPUT1 CPUT1 Pwrdwn drive mode Driven in power down Tristate in power down RW 0
1 CPUT0 CPUT0 Pwrdwn drive mode Driven in power down Tristate in power down RW 0
0 DOT96T DOT96 power down drive mode Driven in power down Tristate RW 0
BYTE 0
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 CPUT2, CPUC2/ Output enable Tristate Enable RW 1
SRCT7, SRCC7
6 SRCT6, SRCC6 Output enable Tristate Enable RW 1
5 SRCT5, SRCC5 Output enable Tristate Enable RW 1
4 SRCT4, SRCC4 (SATA) Output enable Tristate Enable RW 1
3 SRCT3, SRCC3 Output enable Tristate Enable RW 1
2 SRCT2, SRCC2 Output enable Tristate Enable RW 1
1 SRCT1, SRCC1 Output enable Tristate Enable RW 1
0 REF0 2x drive 2x drive enable 1x 2x RW 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

IDTCV115-2PVG8

Mfr. #:
Buy IDTCV115-2PVG8
Manufacturer:
Description:
IC FLEXPC CLK PROGR P4 56-TSSOP
Lifecycle:
New from this manufacturer.
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