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IDTCV115-2PVG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
COMMERCIAL TEMPERATURE RANGE
10
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
BYTE 24
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 H_CBS1 Hard Alarm CPU PLL mode select RW 0
6 H_CBS0 (see H_CBS Band Selection table) RW 0
5 H_CNS2 Hard Alarm CPU PLL N select RW 0
4 H_CNS0 (see H_CNS N Selection table) RW 0
3 H_PNS1 Hard Alarm SRC PLL RW 0
(PCI Express) N select
2 H_PNS0 (see H_PNS N selection table) RW 0
1 0
0 0
BYTE 26
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 Turbo2 Turbo Enable Disable Enable RW 0
6 RW 0
5 RW 0
4 RW 0
3 Soft Timer 3 (MSB) Soft alarm timer RW 0
2 Soft Timer 2 RW 0
1 Soft Timer 1 RW 0
0 Soft Timer 0 (LSB) RW 1
BYTE 25
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 WD Timer 7 (MSB) Hard Alarm timer RW 0
6 WD Timer 6 Default is 11*290ms RW 0
5 WD Timer 5 RW 0
4 WD Timer 4 RW 0
3 WD Timer 3 RW 1
2 WD Timer 2 RW 0
1 WD Timer 1 RW 1
0 WD Timer 0 (LSB) RW 1
BYTE 27
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 Watch Dog Enable Watch Dog Enable Disable Enable RW 0
6 0
5 Soft Alarm Enable Soft Alarm Enable Disable Enable RW 0
4 Soft RESET# Soft Reset Enable Disable Soft Reset Enable RW 0
3 Hard Alarm Enable Hard Alarm Enable Disable Enable RW 0
2 Hard RESET# Hard Reset Enable Disable Hard Reset Enable RW 0
1 Hard Alarm FS Relatch FS[C, B, A] Disable Relatch RW 0
Relatch Enable at Hard Alarm
0 TCN8 (MSB) RW 0
COMMERCIAL TEMPERATURE RANGE
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
11
BYTE 28
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 TCN7 RW 1
6 TCN6 RW 0
5 TCN5 Turbo CPU PLL N setting RW 0
4 TCN4 CPU Frequency = N * Resolution RW 1
3 TCN3 (see Resolution table) RW 0
2 TCN2 RW 1
1 TCN1 RW 1
0 TCN0 (LSB) RW 0
BYTE 30
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 TPN0 (LSB) 0
6 TCN28 0
5 Test Mode entry control Normal operation Test mode, 0
controlled by byte 30 bit 4
4 Only valid when Byte6 bit5 is high Hi-Z REF/N mode 0
3 PCI4/Turbo 1 PCI4/Turbo Mode select Turbo 1 PCI4 RW 0
2 Turbo 1 Disable Enable RW 0
1 Test_scl On chip test mode enable normal SCLK=1, CLK outputs=1 RW 0
SCLK=0, CLK outputs=0
0 Test_hiz CLK outputs enable normal CLK outputs=Tristate RW 0
BYTE 29
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 TPN8 (MSB) 0
6 TPN7 1
5 TPN6 Turbo SRC PLL N setting 0
4 TPN5 SRC Frequency = N * Resolution 0
3 TPN4 Resolution = 0.666667 1
2 TPN3 0
1 TPN2 1
0 TPN1 1
BYTE 31
Bit Output(s) Affected Description / Function 0 1 Type Power On
7 TCN27 1
6 TCN26 0
5 TCN25 0
4 TCN24 Turbo CPU PLL N setting 1
3 TCN23 0
2 TCN22 1
1 TCN21 1
0 TCN20 0
COMMERCIAL TEMPERATURE RANGE
12
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE
Trigger Watch Dog Circuit
If Soft Alarm Enabled (byte 27):
Set WDSRB (byte 6)
Load CPU N and Mode
selections into PCU PLL
Load SRC N selection
into SRC PLL
If Soft Reset# Enabled (byte 27):
Issue RESET#
If Hard Alarm Enabled (byte 27):
Set WDHRB (byte 6)
Load CPU N and Band selections into PCU PLL
Load SRC N selections into SRC PLL
If Hard Reset# Enabled (byte 27):
Issue RESET#
If Hard Alarm Relatch Enabled:
Latch FSC, B, A
WD SOFT AND HARD ALARM/TIME OUT OPERATION
PLL FREQUENCY PROGRAMMING PROCEDURES
The user changes PLL frequency through Soft Alarm or Hard Alarm. The Watch Dog circuit has to be enabled. Based on their application, the user may
enable either one or both of the alarms.
User presets the CPU PLL Mode and N, and SRC PLL N value:
1. Set CPU PLL Mode, CB1 and CB2, byte17
2. Set CPU PLL N, CN1 and CN2, byte18 and byte19
3. Set SRC(PCI Express) PLL N, PN1 and PN2, byte21, 22
User selects the frequency for Soft Alarm and Hard Alarm, if enabled respectively:
4. Select Soft Alarm frequency, byte23
5. Select Hard Alarm frequency, byte24
User sets the Timer and enables the WD circuit for frequency switch:
6. Set Hard Alarm Timer, byte25
7. Set Soft Alarm Timer, byte 26
8. Enable Soft and Hard Alarm and RESET# bit (If user needs RESET# signal to reset the system), byte27
9. Enable Watch Dog (WDE), byte27
• Soft Reset# and Hard Reset# are valid only if Soft Alarm and Hard Alarm are enabled respectively.
• WDE Disable resets WDSRB and WDHRB.
• PCI CLK is selectable from SRC PLL or SATA PLL, byte5 bit6. If from SRC PLL, PCI frequency = 1/3 of SRC frequency. If from SATA, PCI is
fixed to 3 selections, 33MHz, 36MHz and 40MHz, byte5 bit[5:4].
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

IDTCV115-2PVG8

Mfr. #:
Buy IDTCV115-2PVG8
Manufacturer:
Description:
IC FLEXPC CLK PROGR P4 56-TSSOP
Lifecycle:
New from this manufacturer.
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