Detailed Description
The MAX6952 is a serially interfaced display driver that
can drive four digits of 5
✕
7 cathode-row dot-matrix
displays. The MAX6952 can drive either four monocolor
digits (Table 1) or two bicolor digits (Table 2). The
MAX6952 includes a 128-character font map compris-
ing 104 predefined characters and 24 user-definable
characters. The predefined characters follow the Arial
font, with the addition of the following common sym-
bols: £, €, ¥, °, µ, ±, ↑, and ↓. The 24 user-definable
characters are uploaded by the user into on-chip RAM
through the serial interface and are lost when the
device is powered down. Figure 1 is the MAX6952
functional diagram.
Serial Interface
The MAX6952 communicates through an SPI-compati-
ble 4-wire serial interface. The interface has three
inputs, clock (CLK), chip select (CS), and data in (DIN),
and one output, data out (DOUT). CS must be low to
clock data into or out of the device, and DIN must be
stable when sampled on the rising edge of CLK. DOUT
is stable on the rising edge of CLK. Note that while the
SPI protocol expects DOUT to be high impedance
when the MAX6952 is not being accessed, DOUT on
the MAX6952 is never high impedance.
MAX6952
4-Wire Interfaced, 2.7V to 5.5V,
4-Digit 5
✕
7 Matrix LED Display Driver
_______________________________________________________________________________________ 5
Pin Description
PIN
SSOP PDIP
NAME FUNCTION
1, 2, 3, 6–14, 23, 24 1, 2, 3, 7–15, 26, 27 O0 to O13
LED Cathode Drivers. O0 to O13 outputs sink current from
the display’s cathode rows.
4, 5, 16 4, 5, 6, 18 GND Ground
15 17 ISET
Segment Current Setting. Connect ISET to GND through
series resistor R
SET
to set the peak current.
17 19 BLINK Blink Clock Output. Output is open drain.
18 20 DIN
Serial Data Input. Data is loaded into the internal 16-bit shift
register on the rising edge of the CLK.
19 21 CLK
Serial-Clock Input. On the rising edge of CLK, data is
shifted into the internal shift register. On the falling edge of
CLK, data is clocked out of DOUT. CLK input is active only
while CS is low.
20 22 DOUT
Serial Data Output. Data clocked into DIN is output to
DOUT 15.5 clock cycles later. Data is clocked out on the
rising edge of CLK. Output is push-pull.
21 23 CS
Chip-Select Input. Serial data is loaded into the shift register
while CS is low. The last 16 bits of serial data are latched on
CS’s rising edge.
22 24 OSC
Multiplex Clock Input. To use the internal oscillator, connect
capacitor C
SET
from OSC to GND. To use the external
clock, drive OSC with a 1MHz to 8MHz CMOS clock.
25–31, 34, 35, 36 28–34, 38, 39, 40 O14 to O23
LED Anode Drivers. O14 to O23 outputs source current to
the display’s anode columns.
32, 33 35, 36, 37 V+
Positive Supply Voltage. Bypass V+ to GND with a 47µF
bulk capacitor and a 0.1µF ceramic capacitor.
