DECEMBER 2015
DSC-5279/07
1
©2015 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆
128K x 36, 256K x 18 memory configurations
◆◆
◆◆
◆
Supports high system speed:
Commercial and Industrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
◆◆
◆◆
◆
LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆
3.3V core power supply
◆◆
◆◆
◆
Power down controlled by ZZ input
◆◆
◆◆
◆
3.3V I/O
◆◆
◆◆
◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP)
Pin Description Summary
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V3578.
A
0
-A
17
Address Inputs Input Synchronous
CE
Chip Enable Input Synchronous
CS
0
, CS
1
Chip Selects Input Synchronous
OE
Output Enable Input Asynchronous
GW
Global Write Enable Input Synchronous
BWE
Byte Write Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
(1)
Individual Byte Write Selects Input Synchronous
CLK Clock Input N/A
ADV
Burst Address Advance Input Synchronous
ADSC
Address Status (Cache Controller) Input Synchronous
ADSP
Address Status (Processor) Input Synchronous
LBO
Linear / Interleaved Burst Order Input DC
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output I/O Synchronous
V
DD
, V
DDQ
Core Power, I/O Power Supply N/A
V
SS
Ground Supply N/A
5279 tbl 01
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V3576S
IDT71V3578S
Description
The IDT71V3576/78 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3576/78 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V3576/78 SRAMs utilize the latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
