6.42
10
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
150MHz 133MHz
Symbol Parameter Min. Max. Min. Max. Unit
t
CY C
Clock Cycle Time 6.7
____
7.5
____
ns
t
CH
(1)
Clock High Pulse Width 2.6
____
3
____
ns
t
CL
(1)
Clock Low Pulse Width 2.6
____
3
____
ns
Output Parameters
t
CD
Clock High to Valid Data
____
3.8
____
4.2 ns
t
CDC
Clock High to Data Change 1.5
____
1.5
____
ns
t
CL Z
(2 )
Clock High to Output Active 0
____
0
____
ns
t
CHZ
(2 )
Clock High to Data High-Z 1.5 3.8 1.5 4.2 ns
t
OE
Output Enable Access Time
____
3.8
____
4.2 ns
t
OLZ
(2)
Output Enable Low to Output Active 0
____
0
____
ns
t
OHZ
(2)
Output Enable High to Output High-Z
____
3.8
____
4.2 ns
Set Up Times
t
SA
Address Setup Time 1.5
____
1.5
____
ns
t
SS
Address Status Setup Time 1.5
____
1.5
____
ns
t
SD
Data In Setup Time 1.5
____
1.5
____
ns
t
SW
Write Setup Time 1.5
____
1.5
____
ns
t
SAV
Address Advance Setup Time 1.5
____
1.5
____
ns
t
SC
Chip Enable/Select Setup Time 1.5
____
1.5
____
ns
Hold Times
t
HA
Address Hold Time 0.5
____
0.5
____
ns
t
HS
Address Status Hold Time 0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.5
____
0.5
____
ns
t
HW
Write Hold Time 0.5
____
0.5
____
ns
t
HAV
Address Advance Hold Time 0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
ns
Sleep Mode and Configuration Parameters
t
ZZPW
ZZ Pulse Width 100
____
100
____
ns
t
ZZR
(3 )
ZZ Recovery Time 100
____
100
____
ns
t
CFG
(4)
Configuration Set-up Time 27
____
30
____
ns
5279 tbl 16
