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71V3576S133PFGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
7
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test LoadAC Test Conditions
(VDDQ = 3.3V)
NOTE:
1. The LBO pin will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O
Z
0
=50Ω
5279 drw 06
,
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5279 drw 07
,
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leakage Current V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LZZ
|
ZZ and LBO Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Output Low Voltage I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -8mA, V
DD
= Min. 2.4
___
V
5279 tbl 08
Symbol Parameter Test Conditions
150MHz 133MHz
UnitCom'lIndCom'lInd
I
DD
Operating Power Supply
Current
Device Selected, Outputs Open, VDD = Max.,
V
DDQ = Max., VIN > VIH or < VIL, f = fMAX
(2 )
295 305 250 260 mA
I
SB1 CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
V
DDQ = Max., VIN > VHD or < VLD, f = 0
(2,3)
30 35 30 35 mA
I
SB2 Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
V
DDQ = Max., VIN > VHD or < VLD, f = fMAX
(2,3)
105 115 100 110 mA
I
ZZ
Full Sleep Mode Supply
Current
ZZ >
VHD, VDD = Max.
30 35 30 35 mA
5279 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figure 1
5279 tbl 10
6.42
8
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table
(1,3)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
Operation Address
Used
CE
CS
0
CS
1
ADSP ADSC ADV GW BWE BWx OE
(2)
CLK I/O
Deselected Cycle, Power Down NoneHXXX L XXXXX-HI-Z
Deselected Cycle, Power Down NoneLXHL XXXXXX-HI-Z
Deselected Cycle, Power Down NoneLLX L XXXXXX-HI-Z
Deselected Cycle, Power Down NoneLXHX L XXXXX -HI-Z
Deselected Cycle, Power Down NoneLLXX L XXXXX-HI-Z
Read Cycle, Begin Burst ExternalLHL L XXXXXL -D
OUT
Read Cycle, Begin Burst ExternalLHL L XXXXXH-HI-Z
Read Cycle, Begin Burst External L H L H L X H H X L - D
OUT
Read Cycle, Begin Burst External L H L H L X H L H L - D
OUT
Read Cycle, Begin Burst External L H L H L X H L H H - HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X - D
IN
Write Cycle, Begin Burst External L H L H L X L X X X - D
IN
Read Cycle, Continue Burst Next X X X H H L H H X L - D
OUT
Read Cycle, Continue Burst Next X X X H H L H H X H - HI-Z
Read Cycle, Continue Burst Next X X X H H L H X H L - D
OUT
Read Cycle, Continue Burst Next X X X H H L H X H H - HI-Z
Read Cycle, Continue Burst Next H X X X H L H H X L - D
OUT
Read Cycle, Continue Burst Next H X X X H L H H X H - HI-Z
Read Cycle, Continue Burst Next H X X X H L H X H L - D
OUT
Read Cycle, Continue Burst Next H X X X H L H X H H - HI-Z
Write Cycle, Continue Burst Next X X X H H L H L L X - D
IN
Write Cycle, Continue Burst Next X X X H H L L X X X - D
IN
Write Cycle, Continue Burst Next H X X X H L H L L X - D
IN
Write Cycle, Continue Burst Next H X X X H L L X X X - D
IN
Read Cycle, Suspend Burst Current X X X H H H H H X L - D
OUT
Read Cycle, Suspend Burst Current X X X H H H H H X H - HI-Z
Read Cycle, Suspend Burst Current X X X H H H H X H L - D
OUT
Read Cycle, Suspend Burst Current X X X H H H H X H H - HI-Z
Read Cycle, Suspend Burst Current H X X X H H H H X L - D
OUT
Read Cycle, Suspend Burst Current H X X X H H H H X H - HI-Z
Read Cycle, Suspend Burst Current H X X X H H H X H L - D
OUT
Read Cycle, Suspend Burst Current H X X X H H H X H H - HI-Z
Write Cycle, Suspend Burst Current X X X H H H H L L X - D
IN
Write Cycle, Suspend Burst Current X X X H H H L X X X - D
IN
Write Cycle, Suspend Burst Current H X X X H H H L L X - D
IN
Write Cycle, Suspend Burst Current H X X X H H L X X X - D
IN
5279 tbl 11
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
9
Linear Burst Sequence Table (LBO=VSS)
Synchronous Write Function Truth Table
(1, 2)
Asynchronous Truth Table
(1)
Interleaved Burst Sequence Table (LBO=VDD)
NOTES:
1. L = V
IL, H = VIH, X = Don’t Care.
2. BW
3 and BW4 are not applicable for the IDT71V3578.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation
GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all BytesLXXXXX
Write all BytesHLLLLL
Write Byte 1
(3)
HLLHHH
Write Byte 2
(3)
HLHLHH
Write Byte 3
(3)
HLHHLH
Write Byte 4
(3)
HLHHHL
5279 tbl 12
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1 )
11000110
5279 tbl 15
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1 )
11100100
5279 tbl 14
Operation
(2 )
OE
ZZ I/O Status Power
Read L L Data Out Active
Read H L High-Z Active
Write X L High-Z – Data In Active
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sleep
5279 tbl 13
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

71V3576S133PFGI

Mfr. #:
Buy 71V3576S133PFGI
Manufacturer:
IDT
Description:
SRAM 4M 3.3V I/O PBSRAM SLOW X
Lifecycle:
New from this manufacturer.
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