10 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Signal Type Name/Description
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal Type Name/Description
REFRES[13,12,9:0] I/O External Reference Resistors. Provides a reference for the SerDes bias
currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be
connected from these pins to ground.
REFRESPLL I/O PLL External Reference Resistor. Provides a reference for the PLL bias
currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be
connected from this pin to ground.
V
DD
CORE I Core V
DD.
Power supply for core logic (1.0V).
V
DD
I/O I I/O V
DD.
LVTTL I/O buffer power supply (2.5V or preferred 3.3V).
V
DD
PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).
V
DD
PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).
V
DD
PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
V
SS
I Ground.
Table 7 Power, Ground, and SerDes Resistor Pins
11 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Pin Characteristics
Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to
appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any
of these pins left floating can cause a slight increase in power consumption. Finally, unused Serdes (Rx and Tx) pins should be left floating.
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
PCI Express Interface PE00RN[3:0] I PCIe
Differential
2
Serial Link
PE00RP[3:0] I
PE00TN[3:0] O
PE00TP[3:0] O
PE01RN[3:0] I
PE01RP[3:0] I
PE01TN[3:0] O
PE01TP[3:0] O
PE02RN[3:0] I
PE02RP[3:0] I
PE02TN[3:0] O
PE02TP[3:0] O
PE03RN[3:0] I
PE03RP[3:0] I
PE03TN[3:0] O
PE03TP[3:0] O
PE04RN[3:0] I
PE04RP[3:0] I
PE04TN[3:0] O
PE04TP[3:0] O
PE05RN[3:0] I
PE05RP[3:0] I
PE05TN[3:0] O
PE05TP[3:0] O
PE06RN[3:0] I
PE06RP[3:0] I
PE06TN[3:0] O
PE06TP[3:0] O
PE07RN[3:0] I
PE07RP[3:0] I
PE07TN[3:0] O
PE07TP[3:0] O
PE08RN[3:0] I
PE08RP[3:0] I
PE08TN[3:0] O
Table 8 Pin Characteristics (Part 1 of 3)
12 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
PCI Express Interface
(Cont.)
PE08TP[3:0] O PCIe
Differential
Serial Link
PE09RN[3:0] I
PE09RP[3:0] I
PE09TN[3:0] O
PE09TP[3:0] O
PE12RN[3:0] I
PE12RP[3:0] I
PE12TN[3:0] O
PE12TP[3:0] O
PE13RN[3:0] I
PE13RP[3:0] I
PE13TN[3:0] O
PE13TP[3:0] O
GCLKN[1:0] I HCSL Diff. Clock
Input
Refer to Table 9
GCLKP[1:0] I
P00CLKN,
P00CLKP
I
P02CLKN,
P02CLKP
I
SMBus MSMBCLK I/O LVTTL STI
3
pull-up on board
MSMBDAT I/O STI pull-up on board
SSMBADDR[2:1] I Input pull-up
SSMBCLK I/O STI pull-up on board
SSMBDAT I/O STI pull-up on board
General Purpose I/O GPIO[8:0] I/O LVTTL STI,
High Drive
pull-up
System Pins CLKMODE[1:0] I LVTTL Input pull-up
CLKMODE[2] I pull-down
GCLKFSEL I pull-down
P01MERGEN I pull-down
P23MERGEN I pull-down
P45MERGEN I pull-down
P67MERGEN I pull-down
P89MERGEN I pull-down
P1213MERGEN I pull-down
PERSTN I STI
RSTHALT I Input pull-down
SWMODE[3:0] I pull-down
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
Table 8 Pin Characteristics (Part 2 of 3)

89H48H12G2ZCBL8

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCIE GEN2 SWITCH
Lifecycle:
New from this manufacturer.
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