16 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
T
TX-IDLE-SET-TO-IDLE
Maximum time to transition to a valid Idle after sending
an Idle ordered set
88 ns
T
TX-IDLE-TO-DIFF-
DATA
Maximum time to transition from valid idle to diff data 8 8 ns
T
TX-SKEW
Transmitter data skew between any 2 lanes 1.3 1.3 ns
T
MIN-PULSED
Minimum Instantaneous Lone Pulse Width NA 0.9 UI
T
TX-HF-DJ-DD
Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI
T
RF-MISMATCH
Rise/Fall Time Differential Mismatch NA 0.1 UI
PCIe Receive
UI Unit Interval 399.88 400 400.12 199.94 200.06 ps
T
RX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI
T
RX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation 0.3 UI
T
RX-SKEW
Lane to lane input skew 20 8 ns
T
RX-HF-RMS
1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps
T
RX-HF-DJ-DD
Maximum tolerable DJ by the receiver (common clock) NA 88 ps
T
RX-LF-RMS
10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps
T
RX-MIN-PULSE
Minimum receiver instantaneous eye width NA 0.6 UI
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0
Signal Symbol
Reference
Edge
Min Max Unit
Timing
Diagram
Reference
GPIO
GPIO[8:0]
1
1.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
Tpw
2
2.
The values for this symbol were determined by calculation, not by testing.
None 50 ns
Table 11 GPIO AC Timing Characteristics
Parameter Description
Gen 1 Gen 2
Units
Min
1
Typ
1
Max
1
Min
1
Typ
1
Max
1
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
17 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Figure 5 JTAG AC Timing Waveform
Signal Symbol
Reference
Edge
Min Max Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK Tper_16a none 50.0 ns See Figure 5.
Thigh_16a,
Tlow_16a
10.0 25.0 ns
JTAG_TMS
1
,
JTAG_TDI
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK rising 2.4 ns
Thld_16b 1.0 ns
JTAG_TDO Tdo_16c JTAG_TCK falling 20 ns
Tdz_16c
2
2.
The values for this symbol were determined by calculation, not by testing.
—20ns
JTAG_TRST_N Tpw_16d
2
none 25.0 ns
Table 12 JTAG AC Timing Characteristics
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
18 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Recommended Operating Supply Voltages
Power-Up/Power-Down Sequence
During power supply ramp-up, V
DD
CORE must remain at least 1.0V below V
DD
I/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes 2.25 2.5 2.75 V
3.125 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC value.
PCI Express Analog Power 0.95 1.0 1.1 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 13 PES48H12G2 Operating Voltages
Grade Temperature
Commercial 0
°C to +70°C Ambient
Industrial -40°C to +85°C Ambient
Table 14 PES48H12G2 Operating Temperatures

89H48H12G2ZCBL8

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCIE GEN2 SWITCH
Lifecycle:
New from this manufacturer.
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