19 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Note 1: I/O supply of 3.3V is preferred.
Note 2: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be
reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in V
DD
PEA, V
DD
PEHA, and
V
DD
PETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turned-
off port is close to zero. For example, if 2 ports out of 12 are turned off, then the power savings for each of the above three power rails can be
calculated quite simply as 2/12 multiplied by the power consumption indicated in the above table.
Note 3: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: V
DD
PEA, V
DD
PEHA, and
V
DD
PETA.
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
Power
Max
Power
8/8/8/8/8/8
(Full Swing)
mA 3360 5529 2313 2705 816 825 845 898 24 29
Watts 3.36 6.08 2.31 2.98 2.04 2.27 0.85 0.99 0.06 0.08 8.62 12.40
8/8/8/8/8/8
(Half Swing)
mA 3360 5529 1989 2327 816 825 439 467 24 29
Watts 3.36 6.08 1.99 2.56 2.04 2.27 0.44 0.51 0.06 0.08 7.89 11.50
Table 15 PES48H12G2 Power Consumption — 2.5V I/O
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465V
Typ
Power
Max
Power
8/8/8/8/8/8
(Full Swing)
mA 3360 5529 2313 2705 816 825 845 898 30 35
Watts 3.36 6.08 2.31 2.98 2.04 2.27 0.85 0.99 0.10 0.12 8.66 12.44
8/8/8/8/8/8
(Half Swing)
mA 3360 5529 1989 2327 816 825 439 467 30 35
Watts 3.36 6.08 1.99 2.56 2.04 2.27 0.44 0.51 0.10 0.12 7.93 11.54
Table 16 PES48H12G2 Power Consumption — 3.3V I/O
20 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Thermal Considerations
This section describes thermal considerations for the PES48H12G2 (27mm
2
FCBGA676 package). The data in Table 17 below contains informa-
tion that is relevant to the thermal performance of the PES48H12G2 switch.
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the T
J(max)
value
specified in Table 17. Consequently, the effective junction to ambient thermal resistance (
θ
JA
) for the worst case scenario must be
maintained below the value determined by the formula:
θ
JA
= (T
J(max)
- T
A(max)
)/P
Given that the values of T
J(max)
, T
A(max)
, and P are known, the value of desired θ
JA
becomes a known entity to the system designer. How to
achieve the desired
θ
JA
is left up to the board or system designer, but in general, it can be achieved by adding the effects of θ
JC
(value
provided in Table 17), thermal resistance of the chosen adhesive (
θ
CS
), that of the heat sink (θ
SA
), amount of airflow, and properties of the
circuit board (number of layers and size of the board). It is strongly recommended that users perform their own thermal analysis for their own
board and system design scenarios.
Symbol Parameter Value Units Conditions
T
J(max)
Junction Temperature 125
o
C Maximum
T
A(max)
Ambient Temperature 70
o
C Maximum for commercial-rated products
85
o
C Maximum for industrial-rated products
θ
JA(effective)
Effective Thermal Resistance, Junction-to-Ambient
14.6
o
C/W Zero air flow
7.8
o
C/W 1 m/S air flow
6.4
o
C/W 2 m/S air flow
θ
JB
Thermal Resistance, Junction-to-Board 2.7
o
C/W
θ
JC
Thermal Resistance, Junction-to-Case 0.15
o
C/W
P Power Dissipation of the Device 12.44 Watts Maximum
Table 17 Thermal Specifications for PES48H12G2, 27x27 mm FCBGA676 Package
21 of 44 November 28, 2011
IDT 89HPES48H12G2 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type Parameter Description
Gen1 Gen2 Unit
Condi-
tions
Min
1
Typ
1
Max
1
Min
1
Typ
1
Max
1
Serial Link PCIe Transmit
V
TX-DIFFp-p
Differential peak-to-peak output
voltage
800 1200 800 1200 mV
V
TX-DIFFp-p-LOW
Low-Drive Differential Peak to
Peak Output Voltage
400 1200 400 1200 mV
V
TX-DE-RATIO-
3.5dB
De-emphasized differential output
voltage
-3 -4 -3.0 -3.5 -4.0 dB
V
TX-DE-RATIO-
6.0dB
De-emphasized differential output
voltage
NA -5.5 -6.0 -6.5 dB
V
TX-DC-CM
DC Common mode voltage 0 3.6 0 3.6 V
V
TX-CM-ACP
RMS AC peak common mode
output voltage
20 mV
V
TX-CM-DC-active-
idle-delta
Abs delta of DC common mode
voltage between L0 and idle
100 100 mV
V
TX-CM-DC-line-
delta
Abs delta of DC common mode
voltage between D+ and D-
25 25 mV
V
TX-Idle-DiffP
Electrical idle diff peak output 20 20 mV
RL
TX-DIFF
Transmitter Differential Return
loss
10 10 dB 0.05 - 1.25GHz
8 dB 1.25 - 2.5GHz
RL
TX-CM
Transmitter Common Mode
Return loss
66dB
Z
TX-DIFF-DC
DC Differential TX impedance 80 100 120 120 Ω
VTX-CM-ACpp Peak-Peak AC Common NA 100 mV
V
TX-DC-CM
Transmit Driver DC Common
Mode Voltage
0 3.6 0 3.6 V
V
TX-RCV-DETECT
The amount of voltage change
allowed during Receiver Detec-
tion
600 600 mV
I
TX-SHORT
Transmitter Short Circuit Current
Limit
090 90mA
Table 18 DC Electrical Characteristics (Part 1 of 2)

89H48H12G2ZCBL8

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCIE GEN2 SWITCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union