78Q2123/78Q2133 Data Sheet DS_21x3_001
6 Rev. 1.6
1.1.5 Receive Signal Qualification
The integrated signal qualifier has separate squelch and unsquelch thresholds. It also includes a built-in timer
to ensure fast and accurate signal detection and line noise rejection. Upon detection of two or more valid
10BASE-T or 100BASE-TX pulses on the line receive port, signal detect is indicated. The signal detect
threshold is then lowered by about 40%. All adaptive circuits are released from their initial states and allowed
to lock onto the incoming data. In 100BASE-TX operation, signal detect is de-asserted when no signal is
presented for a period of about 1.2 µs. In 10BASE-T operation, signal detect is de-asserted whenever no
Manchester data is received. In either case, the signal detect threshold will return to the squelched level
whenever the signal detect indication is de-asserted. Signal detect is also used to control the operation of the
clock/data recovery circuit to assure fast acquisition.
1.1.6 Receive Clock Recovery
In 100BASE-TX mode, the 125 MHz receive clock is extracted using a digital DLL-based loop. When no
receive signal is present, the CDR is directed to lock onto the 125 MHz transmit serial clock. When signal
detect is asserted, the CDR will use the received MLT-3 signal as the clock reference. The recovered clock is
used to re-time the data signal and for conversion of the data to NRZ format.
In 10BASE-T mode, the 20 MHz receive clock is recovered digitally from the Manchester data using a
DLL locked to the reference clock. When Manchester-coded preambles are detected, the CDR
immediately re-aligns the phase of the clock to synchronize with the incoming data. Hence clock
acquisition is fast and immediate.
1.2 100BASE-TX OPERATION
1.2.1 100BASE-TX Transmit
The 78Q2123/78Q2133 contain all of the necessary circuitry to convert the transmit MII signaling from a
MAC to an IEEE-802.3 compliant data-stream driving Cat-5 UTP cabling. The internal PCS interface
maps 4 bit nibbles from the MII to 5 bit code groups as defined in Table 24-1 of IEEE-802.3. These 5 bit
code groups are then scrambled and converted to a serial stream before being sent to the MLT-3 pulse
shaping circuitry and line driver. The pulse-shaper uses current modulation to produce the desired output
waveform. Controlled rise/fall time in the MLT-3 signal is achieved using an accurately controlled voltage
ramp generator. The line driver requires an external 1:1 isolation transformer to interface with the line
media. The center-tap of the primary side of the transformer must be connected to the Vcc supply (3.3V
± 0.3V).
1.2.2 100BASE-TX Receive
The 78Q2123/78Q2133 receive a 125MBaud MLT-3 signal through a 1:1 transformer. The signal then
goes through a combination of adaptive offset adjustment (baseline wander correction) and adaptive
equalization. The effect of these circuits is to sense the amount of dispersion and attenuation caused by
the cable and transformer, and restore the received pulses to logic levels. The amount of gain and
equalization applied to the pulses varies with the detected attenuation and dispersion and, therefore, with
the length of the cable. The 78Q2123/78Q2133 can compensate for cable loss of up to 10dB at 16 MHz.
This loss is represented as test_chan_5 in Annex A of the ANSI X3.263:199X. The equalized MLT-3 data
signal is bi-directionally sliced and the resulting NRZI bit-stream is presented to the CDR where it is
re-timed and decoded to NRZ format. The re-timed serial data passes through a serial-to-parallel
converter, then descrambled and aligned into 5 bit code groups. The receive PCS interface maps these
code groups to 4 bit data for the MII as outlined in Table 24-1 in Clause 24 of IEEE-802.3.
1.2.3 PCS Bypass Mode (Auto-negotiate must be off)
The PCS Bypass mode is entered by setting register bit MR 16.1. In this mode the 78Q2123/78Q2133
accept scrambled 5 bit code words at the TX_ER and TXD[3:0] pins, TX_ER being the MSB of the data
input. The 5 bit code groups are converted to MLT-3 signal for transmission.
