DS_21x3_001 78Q2123/78Q2133 Data Sheet
Rev. 1.6 7
The received MLT-3 signal is converted to 5 bit NRZ code groups and output from the RX_ER and
RXD[3:0] pins, RX_ER being the MSB of the data output. The RX_DV and TX_EN pins are unused in
PCS Bypass mode.
1.3 10BASE-T OPERATION
1.3.1 10BASE-T Transmit
The 78Q2123/78Q2133 take 4-bit parallel NRZ data via the MII interface and passes it through a parallel
to serial converter. The data is then passed through a Manchester encoder, pre-emphasis pulse-shaper,
media filter, and finally to the twisted-pair line driver. The pulse-shaper and filter ensure the output
waveforms meet the voltage template and spectral content requirements detailed in Clause 14 of
IEEE-802.3. Interface to the twisted-pair media is through a center-tapped 1:1 transformer. No external
filtering is required. During auto-negotiation and 10BASE-T idle periods, link pulses are transmitted.
The 78Q2123/78Q2133 employ an onboard timer to prevent the MAC from capturing a network through
excessively long transmissions. When this timer expires, the chip enters the jabber state and
transmission is halted. The jabber state is exited after the MII goes idle for 500±250 ms.
1.3.2 10BASE-T Receive
The 78Q2123/78Q2133 receive Manchester-encoded 10BASE-T data through the twisted pair inputs and
re-establishes logic levels through a slicer with a smart squelch function. The slicer automatically adjusts
its level after detection of valid data with the appropriate levels. Data is passed on to the CDR where the
clock is recovered, and the data is re-timed and decoded. From there, data enters the serial-to-parallel
converter for transmission to the MAC via the Media Independent Interface. Interface to the twisted-pair
media is through an external 1:1 transformer. Polarity information is detected and corrected within
internal circuitry.
1.3.3 Polarity Correction
The 78Q2123/78Q2133 are capable of either automatic or manual polarity reversal for 10BASE-T and
auto-negotiation functions. Register bits MR16.5 and MR16.4 control this feature. The default is
automatic mode where MR16.5 is low and MR16.4 indicates if the detection circuitry has inverted the
input signal. To enter manual mode, MR16.5 should be set high and MR16.4 will then control the signal
polarity.
1.3.4 SQE TEST
The 78Q2123/78Q2133 support the Signal Quality Error (SQE) function detailed in IEEE-802.3. At an
interval of 1µs after each negative transition of the TX_EN pin in 10BASE-T mode, the COL pin will go
high for a period of 1 µs. SQE is not signaled during transmission after collision is detected. SQE is
automatically disabled when repeater mode is enabled. This function can be disabled through register bit
MR16.11.
1.3.5 Natural Loopback
When enabled, whenever the 78Q2123/78Q2133 are transmitting and not receiving on the twisted pair
media (10BASE-T Half Duplex mode), data on the TXD3-0 pins are looped back onto the RXD3-0 pins.
During a collision, data from the RXI pins is routed to the RXD3-0 pins. The natural loopback function is
enabled through register bit MR16.10. This feature is off by default.
1.3.6 Repeater Mode
When register bit MR16.15 is set, the 78Q2123/78Q2133 are placed in repeater mode. In this mode, full
duplex operation is prohibited, CRS responds only to receive activity and, in 10BASE-T mode, the SQE
test function is disabled.
78Q2123/78Q2133 Data Sheet DS_21x3_001
8 Rev. 1.6
1.4 Auto-Negotiation
The 78Q2123/78Q2133 support the auto-negotiation functions of Clause 28 of IEEE-802.3 for 10/100
Mbps operation over copper wiring. This function can be enabled via register settings. The
auto-negotiation function defaults to ON and bit MR0.12 (ANEGEN) is high after reset. Software can
disable the auto-negotiation function by writing to bit MR0.12.
The contents of register MR4 are sent to the 78Q2123/78Q2133s link partner during auto-negotiation via
fast link pulse coding.
The default values of the auto-negotiation registers are set as follows:
Register.Bits Function Default Value
0.13 Speed Select 1 (100 BASE TX)
0.12 AN Enable 1 (enabled)
0.8 Duplex 1 (full duplex)
4.8/1.14 100BASE-TX
Full Duplex
1
4.7/1.13 100 BASE-TX 1
4.6/1.12 10 BASE-
T
Full Duplex
1
4.5/1.11 10 BASE-T 1
These default values can be changed by writing different values to the registers, then restarting
auto-negotiation.
With auto-negotiation enabled, the 78Q2123/78Q2133 will start sending fast link pulses at power on, loss
of link or upon a command to restart. At the same time, it will look for either 10BASE-T idle, 100BASE-TX
idle, or fast link pulses from its link partner. If either idle pattern is detected, the 78Q2123/78Q2133
configure themselves in half-duplex mode at the appropriate speed. If it detects fast link pulses, it
decodes and analyzes the link code transmitted by the link partner. When three identical link code words
are received (ignoring the acknowledge bit) the link code word is stored in register MR5. Upon receiving
three more identical link code words, with the acknowledge bit set, the 78Q2123/78Q2133 configure
themselves to the highest priority technology common to the two link partners. The technology priorities
are, in descending order:
100BASE-TX, Full Duplex
100BASE-TX, Half Duplex
10BASE-T, Full Duplex
10BASE-T, Half Duplex
Once auto-negotiation is complete, register bits MR18.11:10 will reflect the actual speed and duplex that
was chosen.
If auto-negotiation fails to establish a link for any reason, register bit MR18.12 will reflect this and auto
negotiation will restart from the beginning. Writing a ‘1’ to bit MR0.9 (RANEG) will also cause
auto-negotiation to restart.
DS_21x3_001 78Q2123/78Q2133 Data Sheet
Rev. 1.6 9
1.5 Media Independent Interface
1.5.1 MII Transmit and Receive Operation
The MII interface on the 78Q2123/78Q2133 provide independent transmit and receive paths for both
10Mb/s and 100Mb/s data rates as described in Clause 22 of the IEEE-802.3 standard.
The transmit clock, TX_CLK, provides the timing reference for the transfer of TX_EN, TXD3-0, and
TX_ER signals from the MAC to the 78Q2123/78Q2133. TXD3-0 is captured on the rising edge of
TX_CLK when TX_EN is asserted. TX_ER is also captured on the rising edge of TX_CLK and is
asserted by the MAC to request that an error code group is to be transmitted. The assertion of TX_ER is
ignored when the 78Q2123/78Q2133 are operating in 10BASE-T mode.
The receive clock, RX_CLK, provides the timing reference to transfer RX_DV, RXD3-0, and RX_ER
signals from the 78Q2123/78Q2133 to the MAC. RX_DV transitions synchronously with respect to
RX_CLK and is asserted when the 78Q2123/78Q2133 are presenting valid data on RXD3-0. RX_ER is
asserted and is synchronous to RX_CLK when a code group violation has been detected in the current
receive packet.
1.5.2 Station Management Interface
The station management interface consists of circuitry which implements the serial protocol as described
in Clause 22.2.4.4 of IEEE-802.3. A 16-bit shift register receives serial data applied to the MDIO pin at
the rising-edge of the MDC clock signal. Once the preamble is received, the station management control
logic looks for the start-of-frame sequence and a read or write op-code, followed by the PHYAD and
REGAD fields. The default address for the 78Q2123/78Q2133 is 1. For a read operation, the MDIO port
becomes enabled as an output and the register data is loaded into a shift register for transmission. The
78Q2123/78Q2133 can work with a one-bit preamble rather than the 32 bits prescribed by IEEE-802.3.
This allows for faster programming of the registers. If a register does not exist at an address indicated by
the REGAD field or if the PHYAD field does not match the 78Q2123/78Q2133 PHYAD, a read of the
MDIO port will return all ones. For a write operation, the data is shifted in and loaded into the appropriate
register after the sixteenth data bit has been received. Writes to registers not supported by the
78Q2123/78Q2133 are ignored.
When the PHYAD field is all zeros, the Station Management Entity (STA) is requesting a broadcast data
transaction. All PHYs sharing the same Management Interface must respond to this broadcast request.
The 78Q2123/78Q2133 will respond to the broadcast data transaction.

78Q2123S/F

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Ethernet ICs 10/100 Base Tx Transcvr w/MDIX
Lifecycle:
New from this manufacturer.
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