Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. C
05/24/2013
IS62/65WV2568DALL
IS62/65WV2568DBLL
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
256K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 35ns, 45ns, 55ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
– 1.8V ± 10% V
cc (IS62/65WV2568DALL)
– 2.5V–3.6V Vcc (IS62/65WV2568DBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
• Lead-free available
DESCRIPTION
The ISSI IS62/65WV2568DALL and IS62/65WV2568DBLL
are high-speed, 2M bit static RAMs organized as
256K words by 8 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) , the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62/65WV2568DALL and IS62/65WV2568DBLL are
packaged in the JEDEC standard 32-pin TSOP (TYPE I),
sTSOP (TYPE I), and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
JUNE 2013
A0-A17
CS1
OE
WE
256K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CS2
