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IS62WV2568DBLL-45HLI-TR

P1-P3P4-P6P7-P9P10-P12P13-P14
IS62/65WV2568DALL,  IS62/65WV2568DBLL 
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  C
05/24/2013
AC TEST LOADS
Figure 1
Figure 2
CAPACITANCE
(1)
  Symbol  Parameter  Conditions  Max.  Unit
  cIn Input Capacitance VIn = 0V 8 pF
cout Input/Output Capacitance Vout = 0V 10 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
  Parameter  62WV2568DALL  62WV2568DBLL       
    (Unit)  (Unit)
  Input Pulse Level 0.4V to Vcc-0.2V 0.4V to Vcc-0.3V
Input Rise and Fall Times 5 ns 5ns
Input and Output Timing Vref Vref
and Reference Level
Output Load See Figures 1 and 2 See Figures 1 and 2
    1.8V ± 10%   2.5V - 3.6V
  r1(Ω) 3070 3070
R2(Ω) 3150 3150
Vref 0.9V 1.5V
Vtm 1.8V 2.8V
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
IS62/65WV2568DALL,  IS62/65WV2568DBLL 
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev.  C
05/24/2013
POWER SUPPLY CHARACTERISTICS
(1)
 (Over Operating Range)
  Symbol  Parameter  Test Conditions    Max.  Max.  Max.  Unit
          35ns  45ns  55ns
Icc Vcc Dynamic Operating Vcc = Max., Com. 15 12 10 mA
Supply Current Iout = 0 mA, f = fmAx Ind. 20 15 12
Auto. 25 20 15
typ.
(2)
10 8 6
ISB1 TTL Standby Current CS2 = VIL Com. 0.1 0.1 0.1 mA
(TTL Inputs) f = 0Hz Ind. 0.2 0.2 0.2
Auto. 0.3 0.3 0.3
 
ISB2 CMOS Standby (1) 0V < CS2 < 0.2V Com. 7 7 7 µA
Current (CMOS Inputs) OR Ind. 10 10 10
(2) CS1 > VDD - 0.2V,
Auto.
– 30 30
cS2
> VDD - 0.2V typ.
(2)
3
f= 0Hz
Note:
1. At f = f
mAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
cc = 3.0V, Ta = 25
o
C and not 100% tested.
IS62/65WV2568DALL,  IS62/65WV2568DBLL 
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  C
05/24/2013
AC WAVEFORMS
READ CYCLE NO. 1
(1,2) 
(Address Controlled) (CS1 = OE = VIL, cS2 = WE = VIh)
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
READ CYCLE SWITCHING CHARACTERISTICS
(1)
 (Over Operating Range)
Symbol Parameter
35ns 45ns 55ns
UnitMin. Max. Min. Max. Min. Max.
trc Read Cycle Time 35 — 45 — 55 — ns
tAA Address Access Time — 35 — 45 — 55 ns
t
ohA Output Hold Time 10 — 10 — 10 — ns
t
AcS1/tAcS2
CS1/CS2 Access Time
— 35 — 45 — 55 ns
t
Doe
OE Access Time
— 15 — 20 — 25 ns
t
hzoe
(2)
OE to High-Z Output
— 10 — 15 — 20 ns
t
Lzoe
(2)
OE to Low-Z Output
5 — 5 — 5 — ns
t
hzcS1/thzcS2
(2)
CS1/CS2 to High-Z Output
0 10 0 15 0 20 ns
t
LzcS1/tLzcS2
(2)
CS1/CS2 to Low-Z Output
10 — 10 — 10 — ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
P1-P3P4-P6P7-P9P10-P12P13-P14

IS62WV2568DBLL-45HLI-TR

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Description:
SRAM 2Mb 256K x 845ns Async SRAM
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