IS62/65WV2568DALL, IS62/65WV2568DBLL
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/24/2013
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
Symbol Parameter
35ns 45ns 55ns
UnitMin. Max. Min. Max. Min. Max.
tWc Write Cycle Time 35 — 45 — 55 — ns
tScS1/tscs2
CS1/CS2 to Write End
25 — 35 — 45 — ns
tAW Address Setup Time to Write End 25 — 35 — 45 — ns
t
hA Address Hold from Write End 0 — 0 — 0 — ns
t
SA Addrress Setup Time 0 — 0 — 0 — ns
t
PWe
WE Pulse Width
30 — 35 — 40 — ns
t
SD Data Setup to Write End 15 — 20 — 25 — ns
thD Data Hold from Write End 0 — 0 — 0 — ns
t
hzWe
WE LOW to High-Z Output
— 20 — 20 — 20 ns
tLzWe
WE HIGH to Low-Z Output
5 — 5 — 5 — ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
