74LVC74A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 5 April 2013 5 of 18
NXP Semiconductors
74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C the value of P
tot
derates linearly with 8 mW/K.
For TSSOP14 packages: above 60 C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C the value of P
tot
derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input clamping current V
I
< 0 V 50 - mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output clamping current V
O
> V
CC
or V
O
< 0 V - 50 mA
V
O
output voltage
[2]
0.5 V
CC
+ 0.5 V
I
O
output current V
O
= 0 V to V
CC
- 50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[3]
- 500 mW
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage for maximum speed performance 1.65 - 3.6 V
for low-voltage applications 1.2 - 3.6 V
V
I
input voltage 0 - 5.5 V
V
O
output voltage 0 - V
CC
V
T
amb
ambient temperature 40 - +125 C
t/V input transition rise and
fall rate
V
CC
= 1.65 V to 2.7 V 0 - 20 ns/V
V
CC
= 2.7 V to 3.6 V 0 - 10 ns/V
