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74LVC74AD-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
74LVC74A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 5 April 2013 6 of 18
NXP Semiconductors
74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
9. Static characteristics
[1] All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
=25C.
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
V
IH
HIGH-level
input voltage
V
CC
= 1.2 V 1.08 - - 1.08 - V
V
CC
= 1.65 V to 1.95 V 0.65 V
CC
- - 0.65 V
CC
-V
V
CC
= 2.3 V to 2.7 V 1.7 - - 1.7 - V
V
CC
= 2.7 V to 3.6 V 2.0 - - 2.0 - V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V - - 0.12 - 0.12 V
V
CC
= 1.65 V to 1.95 V - - 0.35 V
CC
-0.35 V
CC
V
V
CC
= 2.3 V to 2.7 V - - 0.7 - 0.7 V
V
CC
= 2.7 V to 3.6 V - - 0.8 - 0.8 V
V
OH
HIGH-level
output
voltage
V
I
=V
IH
or V
IL
I
O
= 100 A;
V
CC
=1.65Vto3.6V
V
CC
0.2 - - V
CC
0.3 - V
I
O
= 4mA; V
CC
= 1.65 V 1.2 - - 1.05 - V
I
O
= 8mA; V
CC
= 2.3 V 1.8 - - 1.65 - V
I
O
= 12 mA; V
CC
= 2.7 V 2.2 - - 2.05 - V
I
O
= 18 mA; V
CC
= 3.0 V 2.4 - - 2.25 - V
I
O
= 24 mA; V
CC
= 3.0 V 2.2 - - 2.0 - V
V
OL
LOW-level
output
voltage
V
I
=V
IH
or V
IL
I
O
= 100 A;
V
CC
= 1.65 V to 3.6 V
- - 0.2 - 0.3 V
I
O
=4mA; V
CC
= 1.65 V - - 0.45 - 0.65 V
I
O
=8mA; V
CC
= 2.3 V - - 0.6 - 0.8 V
I
O
=12mA; V
CC
= 2.7 V - - 0.4 - 0.6 V
I
O
=24mA; V
CC
= 3.0 V - - 0.55 - 0.8 V
I
I
input leakage
current
V
CC
= 3.6 V; V
I
=5.5VorGND - 0.1 5- 20 A
I
CC
supply
current
V
CC
= 3.6 V; V
I
=V
CC
or GND;
I
O
=0A
-0.110-40A
I
CC
additional
supply
current
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
=V
CC
0.6 V; I
O
=0A
- 5 500 - 5000 A
C
I
input
capacitance
V
CC
= 0 V to 3.6 V;
V
I
=GNDtoV
CC
-4.0---pF
74LVC74A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 5 April 2013 7 of 18
NXP Semiconductors
74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation
delay
nCP to nQ, nQ; see Figure 7
[2]
V
CC
= 1.2 V - 15 - - - ns
V
CC
= 1.65 V to 1.95 V 1.0 5.0 10.3 1.0 11.9 ns
V
CC
= 2.3 V to 2.7 V 1.8 2.9 5.8 1.8 6.7 ns
V
CC
= 2.7 V 1.0 2.7 6.0 1.0 7.5 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.6 5.2 1.0 6.5 ns
nS
DtonQ, nQ; see Figure 8
V
CC
= 1.2 V - 15 - - - ns
V
CC
= 1.65 V to 1.95 V 0.5 4.0 10.6 0.5 12.2 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns
V
CC
= 2.7 V 1.0 2.9 6.4 1.0 8.0 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns
nR
D to nQ, nQ; see Figure 8
V
CC
= 1.2 V - 15 - - - ns
V
CC
= 1.65 V to 1.95 V 0.5 4.1 10.7 0.5 12.4 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns
V
CC
= 2.7 V 1.0 3.0 6.4 1.0 8.0 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns
t
W
pulse width clock HIGH or LOW; see Figure 7
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
= 2.7 V 3.3 - - 4.5 - ns
V
CC
= 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns
set or reset LOW; see Figure 8
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
= 2.7 V 3.3 - - 4.5 - ns
V
CC
= 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns
t
rec
recovery time set or reset; see Figure 8
V
CC
= 1.65 V to 1.95 V 1.5 - - 1.5 - ns
V
CC
= 2.3 V to 2.7 V 1.5 - - 1.5 - ns
V
CC
= 2.7 V 1.5 - - 1.0 - ns
V
CC
= 3.0 V to 3.6 V +1.0 3.0 - 1.0 - ns
74LVC74A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 5 April 2013 8 of 18
NXP Semiconductors
74LVC74A-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
t
su
set-up time nD to nCP; see Figure 7
V
CC
= 1.65 V to 1.95 V 3.0 - - 3.0 - ns
V
CC
= 2.3 V to 2.7 V 2.5 - - 2.5 - ns
V
CC
= 2.7 V 2.2 - - 2.2 - ns
V
CC
= 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns
t
h
hold time nD to nCP; see Figure 7
V
CC
= 1.65 V to 1.95 V 2.0 - - 2.0 - ns
V
CC
= 2.3 V to 2.7 V 1.5 - - 1.5 - ns
V
CC
= 2.7 V 1.0 - - 1.0 - ns
V
CC
= 3.0 V to 3.6 V +1.0 0.2 - 1.0 - ns
f
max
maximum
frequency
nCP; see Figure 7
V
CC
= 1.65 V to 1.95 V 100 - - 80 - MHz
V
CC
= 2.3 V to 2.7 V 125 - - 100 - MHz
V
CC
= 2.7 V 150 - - 120 - MHz
V
CC
= 3.0 V to 3.6 V 150 250 - 120 - MHz
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power
dissipation
capacitance
per flip-flop; V
I
=GNDtoV
CC
[4]
V
CC
= 1.65 V to 1.95 V - 12.4 - - - pF
V
CC
= 2.3 V to 2.7 V - 16.0 - - - pF
V
CC
= 3.0 V to 3.6 V - 19.1 - - - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
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74LVC74AD-Q100J

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Buy 74LVC74AD-Q100J
Manufacturer:
Nexperia
Description:
Flip Flops 74LVC74AD-Q100/SO14/REEL 13" Q
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