24VL024/24VL025
DS22130A-page 4 © 2009 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
In
SDA
Out
WP
5
7
6
15
3
2
89
13
D4
4
10
11
12
14
© 2009 Microchip Technology Inc. DS22130A-page 5
24VL024/24VL025
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
CC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2 SCL Serial Clock
The SCL input is used to synchronize the data transfer
to and from the device.
2.3 A0, A1, A2
The A0, A1 and A2 inputs are used by the 24VL024/
24VL025 for multiple device operations. The levels on
these inputs are compared with the corresponding bits
in the slave address. The chip is selected if the
compare is true.
Up to eight 24VL024/24VL025 devices (four for the
SOT-23 package) may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V
CC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic1
before normal device operation can proceed.
2.4 WP (24VL024 only)
WP is the hardware write-protect pin. It must be tied to
V
CC or VSS. If tied to VCC, the hardware write protection
is enabled and will protect the entire array (00h-FFh). If
the WP pin is tied to V
SS the hardware write protection
is disabled.
2.5 Noise Protection
The 24VL024/24VL025 employs a VCC threshold
detector circuit that disables the internal erase/write
logic if the V
CC is below 1.0 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits that suppress noise spikes to assure
proper device operation even on a noisy bus.
Name
8-pin
PDIP
8-pin
SOIC
8-pin
TSSOP
8-pin
MSOP
8-pin
TDFN
6-pin
SOT-23
Function
A0 111115User Configurable Chip Select
A1 222224User Configurable Chip Select
A2 3 3 3 3 3 User Configurable Chip Select
V
SS 444442Ground
SDA 555553Serial Data
SCL 666661Serial Clock
WP 7 7 7 7 7 Write-Protect Input
V
CC 888886+1.5V to 3.6V
24VL024/24VL025
DS22130A-page 6 © 2009 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The 24VL024/24VL025 supports a bidirectional, 2-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device that generates the Serial
Clock (SCL), controls the bus access and generates
the Start and Stop conditions, while the 24VL024/
24VL025 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.

24VL025T/MNY

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 2K 256 X 8 SERIAL EE 1.5V
Lifecycle:
New from this manufacturer.
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