Functional Description
The TwinDie DDR3L SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 8-bank DDR3L SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like die tested within a monolithic die package.
The DDR3L SDRAM uses a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3L SDRAM input receiver. DQS is center-aligned with da-
ta for WRITEs. The read data is transmitted by the DDR3L SDRAM and edge-aligned to
the data strobes.
Read and write accesses to the DDR3L SDRAM are burst-oriented. Accesses start at a
selected location and continue for a programmed number of locations in a program-
med sequence. Accesses begin with the registration of an ACTIVATE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits (including CSn#, BAn, and An) registered coincident with the READ or
WRITE command are used to select the rank, bank, and starting column location for the
burst access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR3L data sheet for complete information re-
garding individual die initialization, register definition, command descriptions, and die
operation.
Industrial Temperature
The industrial temperature (IT) option, if offered, requires that the case temperature
not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when
T
C
exceeds 85°C; this also requires use of the high-temperature self refresh option. Addi-
tionally, ODT resistance, I
DD
values, some IDD specifications and the input/output im-
pedance must be derated when T
C
is < 0°C or > 95°C. See the DDR3 monolithic data
sheet for details.
16Gb: x4, x8 TwinDie DDR3L SDRAM
Functional Description
PDF: 09005aef862e2c0a
DDR3L_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. B 03/15 EN
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© 2014 Micron Technology, Inc. All rights reserved.
