PTN3361BBS,518 Datasheet PTN3361BBS,518 | P16-P18

Product data sheet Rev. 02 — 7 October 2009 16 of 29

NXP Semiconductors

PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.7 Characteristics of the I

C-bus

The I

C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.7.1 Bit transfer

One data bit is transferred during each clock phase. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at this

time will be interpreted as control signals (see Figure 5).

7.7.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P). See Figure 6.

7.7.3 System conﬁguration

An I

C-bus device generating a message is a ‘transmitter’, a device receiving is the

‘receiver’. The device that controls the message is the ‘master’ and the devices which are

controlled by the master are the ‘slaves’. See Figure 7.

Fig 5. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 6. Deﬁnition of START and STOP conditions.

mba608

SDA

SCL

STOP condition

START condition

Product data sheet Rev. 02 — 7 October 2009 17 of 29

NXP Semiconductors

PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.7.4 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also, a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating as

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 7. System conﬁguration

002aaa381

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

Fig 8. Acknowledgement on the I

C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 02 — 7 October 2009 18 of 29

NXP Semiconductors

PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

8. Application design-in information

8.1 Dongle or cable adaptor detect discovery mechanism

The PTN3361B supports the source-side dongle detect discovery mechanism described

VESA DisplayPort Interoperability Guideline Version 1.1

When a source-side cable adaptor is plugged into a multi-mode source device that

supports multiple standards such as DisplayPort, DVI and HDMI, a discovery mechanism

is needed for the multi-mode source to conﬁgure itself for outputting DisplayPort, DVI or

HDMI compliant signals through the dongle or cable adaptor. The discovery mechanism

ensures that a multi-mode source device only sends either DVI or HDMI signals when a

valid DVI or HDMI cable adaptor is present.

The V

ESA Interoperability Guideline

recommends that a multi-mode source to power up

with both DDC and AUX CH disabled. After initialization, the source device can use a

variety of mechanisms to decide whether a dongle or cable adaptor is present by

detecting pin 13 on the DisplayPort connector. Depending on the voltage level detected at

pin 13, the source conﬁgures itself either:

• as a DVI or HDMI source (see below paragraph for detection between DVI and HDMI),

and enables DDC, while keeping AUX CH disabled, or

• as a DisplayPort source and enables AUX CH, while keeping DDC disabled.

The monitoring of the voltage level on pin 13 by a multi-mode source device is optional. A

multi-mode source may also e.g. attempt an AUX CH read transaction and, if the

transaction fails, a DDC transaction to discover the presence/absence of a cable adaptor.

Furthermore, a source that supports both DVI and HDMI can discover whether a DVI or

HDMI dongle or cable adaptor is present by using a variety of discovery procedures. One

possible method is to check the voltage level of pin 14 of the DisplayPort connector.

Pin 14 also carries CEC signal used for HDMI. Please note that other HDMI devices on

the CEC line may be momentarily pulling down pin 14 as a part of CEC protocol.

The

VESA Interoperability Guideline

recommends that a multi-mode source should

distinguish a source-side HDMI cable adaptor from a DVI cable adaptor by checking the

DDC buffer ID as described in Section 7.6 “I

C-bus based HDMI dongle detection”. While

it is optional for a multi-mode source to use the I

C-bus based HDMI dongle detection

mechanism, it is mandatory for HDMI dongle or cable adaptor to respond to the I

C-bus

read command described in Section 7.7. The PTN3361B provides an integrated I

C-bus

slave ROM to support this mandatory HDMI dongle detect mechanism for HDMI dongles.

For a DisplayPort-to-HDMI source-side dongle or cable adaptor, DDET must be tied HIGH

to enable the I

C-bus based HDMI dongle detection response function of PTN3361B. For

a DisplayPort-to-DVI sink-side dongle or cable adaptor, DDET must be tied LOW to

disable the function.

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PTN3361BBS,518

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