OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

PTN3361BBS,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
PTN3361B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 7 October 2009 7 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
6.2 Pin description
Table 2. Pin description
Symbol Pin Type Description
OE_N, IN_Dx and OUT_Dx signals
OE_N 25 3.3 V low-voltage
CMOS single-ended
input
Output Enable and power saving function for
high-speed differential level shifter path.
When OE_N = HIGH:
IN_Dx termination = high-impedance
OUT_Dx outputs = high-impedance; zero
output current
When OE_N = LOW:
IN_Dx termination = 50 Ω
OUT_Dx outputs = active
IN_D4+ 48 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D4+ makes a differential pair with IN_D4−.
The input to this pin must be AC coupled
externally.
IN_D4− 47 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D4− makes a differential pair with IN_D4+.
The input to this pin must be AC coupled
externally.
IN_D3+ 45 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D3+ makes a differential pair with IN_D3−.
The input to this pin must be AC coupled
externally.
IN_D3− 44 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D3− makes a differential pair with IN_D3+.
The input to this pin must be AC coupled
externally.
IN_D2+ 42 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D2+ makes a differential pair with IN_D2−.
The input to this pin must be AC coupled
externally.
IN_D2− 41 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D2− makes a differential pair with IN_D2+.
The input to this pin must be AC coupled
externally.
IN_D1+ 39 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D1+ makes a differential pair with IN_D1−.
The input to this pin must be AC coupled
externally.
PTN3361B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 7 October 2009 8 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
IN_D1− 38 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signalling.
IN_D1− makes a differential pair with IN_D1+.
The input to this pin must be AC coupled
externally.
OUT_D4+ 13 TMDS differential
output
HDMI compliant TMDS output. OUT_D4+ makes
a differential pair with OUT_D4−. OUT_D4+ is in
phase with IN_D4+.
OUT_D4− 14 TMDS differential
output
HDMI compliant TMDS output. OUT_D4− makes
a differential pair with OUT_D4+. OUT_D4− is in
phase with IN_D4−.
OUT_D3+ 16 TMDS differential
output
HDMI compliant TMDS output. OUT_D3+ makes
a differential pair with OUT_D3−. OUT_D3+ is in
phase with IN_D3+.
OUT_D3− 17 TMDS differential
output
HDMI compliant TMDS output. OUT_D3− makes
a differential pair with OUT_D3+. OUT_D3− is in
phase with IN_D3−.
OUT_D2+ 19 TMDS differential
output
HDMI compliant TMDS output. OUT_D2+ makes
a differential pair with OUT_D2−. OUT_D2+ is in
phase with IN_D2+.
OUT_D2− 20 TMDS differential
output
HDMI compliant TMDS output. OUT_D2− makes
a differential pair with OUT_D2+. OUT_D2− is in
phase with IN_D2−.
OUT_D1+ 22 TMDS differential
output
HDMI compliant TMDS output. OUT_D1+ makes
a differential pair with OUT_D1−. OUT_D1+ is in
phase with IN_D1+.
OUT_D1− 23 TMDS differential
output
HDMI compliant TMDS output. OUT_D1− makes
a differential pair with OUT_D1+. OUT_D1− is in
phase with IN_D1−.
HPD and DDC signals
HPD_SINK 30 5 V CMOS
single-ended input
0 V to 5 V (nominal) input signal. This signal
comes from the DVI or HDMI sink. A HIGH value
indicates that the sink is connected; a LOW
value indicates that the sink is disconnected.
HPD_SINK is pulled down by an integrated
200 kΩ pull-down resistor.
HPD_SOURCE 7 3.3 V CMOS
single-ended output
0 V to 3.3 V (nominal) output signal. This is
level-shifted version of the HPD_SINK signal.
SCL_SOURCE 9 single-ended 3.3 V
open-drain DDC I/O
3.3 V source-side DDC clock I/O. Pulled up by
external termination to 3.3 V.
SDA_SOURCE 8 single-ended 3.3 V
open-drain DDC I/O
3.3 V source-side DDC data I/O. Pulled up by
external termination to 3.3 V.
SCL_SINK 28 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC clock I/O. Pulled up by
external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
SDA_SINK 29 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC data I/O. Pulled up by
external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
Table 2. Pin description
…continued
Symbol Pin Type Description
PTN3361B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 7 October 2009 9 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
[1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is
disabled.
When DDC_EN = HIGH, buffer and level shifter
are enabled.
Supply and ground
V
DD
2, 11,
15, 21,
26, 33,
40, 46
3.3 V DC supply Supply voltage; 3.3 V ± 10 %.
V
CC
-
GND
[1]
1, 5,
12, 18,
24, 27,
31, 36,
37, 43
ground Supply ground. All GND pins must be connected
to ground for proper operation.
Feature control signals
REXT 6 analog I/O Current sense port used to provide an accurate
current reference for the differential outputs
OUT_Dx. For best output voltage swing
accuracy, use of a 10 kΩ resistor (1 % tolerance)
from this terminal to GND is recommended. May
also be left open-circuit or tied to either V
DD
or
GND. See
Section 7.2 for details.
DDET 4 3.3 V input Dongle detect enable input. When HIGH, the
dongle detect function via I
2
C is active. When
used in an HDMI dongle, this pin must be tied
HIGH for correct operation in accordance with
DisplayPort interoperability guidelines. When
used in a DVI dongle, this pin must be tied LOW.
When LOW, the dongle detect function will not
respond to an I
2
C-bus command. Must be tied to
GND or V
DD
either directly or via a resistor. Note
that this pin may not be left open-circuit.
PES1 10 3.3 V CMOS input Programming pins to activate the pre-emphasis
feature of the TMDS differential outputs. See
Section 7.3 for details. Must be tied either to
GND or V
DD
either directly or via a resistor. To
disable pre-emphasis, connect both to GND
(PES[1:0] = 00b). PES[1:0] = 11b is reserved for
testing purposes and should not be used in
normal application. Note that these pins may not
be left open-circuit.
PES0 3 3.3 V CMOS input
Miscellaneous
n.c. 34, 35 no connection
to the die
Not connected. May be left open-circuit or tied to
GND or V
DD
either directly or via a resistor.
Table 2. Pin description
…continued
Symbol Pin Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

PTN3361BBS,518

Mfr. #:
Buy PTN3361BBS,518
Manufacturer:
NXP Semiconductors
Description:
Buffers & Line Drivers IC LEVEL SHIFTER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet