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PTN3361BBS,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
PTN3361B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 7 October 2009 19 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
9. Limiting values
[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,
Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
[1] Input signals to these pins must be AC-coupled.
[2] Operation without external reference resistor is possible but will result in reduced output voltage swing
accuracy. For details, see Section 7.2.
10.1 Current consumption
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage −0.3 +4.6 V
V
I
input voltage 3.3 V CMOS inputs −0.3 V
DD
+ 0.5 V
5.0 V CMOS inputs −0.3 6.0 V
T
stg
storage temperature −65 +150 °C
V
ESD
electrostatic discharge
voltage
HBM
[1]
- 7000 V
CDM
[2]
- 1000 V
Table 8. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 3.0 3.3 3.6 V
V
I
input voltage 3.3 V CMOS inputs 0 - 3.6 V
5.0 V CMOS inputs 0 - 5.5 V
V
I(AV)
average input voltage IN_Dn+, IN_Dn− inputs
[1]
-0 -V
R
ref(ext)
external reference
resistance
connected between pin
REXT (pin 6) and GND
[2]
-10± 1% - kΩ
T
amb
ambient temperature operating in free air −40 - +85 °C
Table 9. Current consumption
Symbol Parameter Conditions Min Typ Max Unit
I
DD
supply current OE_N = 1 and DDC_EN = 0;
Standby mode
--2mA
OE_N = 0; Active mode - 27 50 mA
PTN3361B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 7 October 2009 20 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
11. Characteristics
11.1 Differential inputs
[1] UI (unit interval) = t
bit
(bit time).
[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 1.65 Gbit/s per lane. Nominal UI at
1.65 Gbit/s = 606 ps.
[3] V
RX_DIFFp-p
= 2 ×|V
RX_D+
− V
RX_D−
|. Applies to IN_Dx signals.
[4] V
i(cm)M(AC)
= |V
RX_D+
+V
RX_D−
| /2− V
RX(cm)
.
V
RX(cm)
= DC (avg) of |V
RX_D+
+V
RX_D−
| /2.
[5] Intended to limit power-up stress on chip set’s PCIe output buffers.
[6] Differential inputs will switch to a high-impedance state when OE_N is HIGH.
Table 10. Differential input characteristics for IN_Dx signals
Symbol Parameter Conditions Min Typ Max Unit
UI unit interval
[1] [2]
600 - 4000 ps
V
RX_DIFFp-p
differential input peak-to-peak voltage
[3]
0.175 - 1.200 V
T
RX_EYE
receiver eye time minimum eye width at
IN_Dx input pair
0.8 - - UI
V
i(cm)M(AC)
peak common-mode input voltage (AC) includes all frequencies
above 30 kHz
[4]
- - 100 mV
Z
RX_DC
DC input impedance 40 50 60 Ω
V
RX(bias)
bias receiver voltage
[5]
1.0 1.2 1.4 V
Z
I(se)
single-ended input impedance inputs in
high-impedance state
[6]
100 - - kΩ
PTN3361B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 7 October 2009 21 of 29
NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
11.2 Differential outputs
The level shifter’s differential outputs are designed to meet HDMI version 1.3 and
DVI version 1.0 specifications.
[1] V
TT
is the DC termination voltage in the HDMI or DVI sink. V
TT
is nominally 3.3 V.
[2] The open-drain output pulls down from V
TT
.
[3] Swing down from TMDS termination voltage (3.3 V ± 10 %).
[4] This differential skew budget is in addition to the skew presented between IN_D+ and IN_D− paired input pins.
[5] This lane-to-lane skew budget is in addition to skew between differential input pairs.
[6] Jitter budget for differential signals as they pass through the level shifter.
11.3 HPD_SINK input, HPD_SOURCE output
[1] Low-speed input changes state on cable plug/unplug.
[2] Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.
[3] Time required to transition from V
OH
to V
OL
or from V
OL
to V
OH
.
[4] Guarantees HPD_SINK is LOW when no display is plugged in.
Table 11. Differential output characteristics for OUT_Dx signals
Symbol Parameter Conditions Min Typ Max Unit
V
OH(se)
single-ended HIGH-level
output voltage
PES[1:0] = 00b
[1]
V
TT
− 0.01 V
TT
V
TT
+ 0.01 V
V
OL(se)
single-ended LOW-level
output voltage
PES[1:0] = 00b
[2]
V
TT
− 0.60 V
TT
− 0.50 V
TT
− 0.40 V
∆V
O(se)
single-ended output
voltage variation
logic 1 and logic 0 state applied
respectively to differential inputs
IN_Dn; R
ref(ext)
connected;
see
Table 8
[3]
450 500 600 mV
I
OZ
OFF-state output current single-ended - - 10 µA
t
r
rise time 20 % to 80 % 75 - 240 ps
t
f
fall time 80 % to 20 % 75 - 240 ps
t
sk
skew time intra-pair
[4]
- - 10 ps
inter-pair
[5]
- - 250 ps
t
jit
jitter time jitter contribution
[6]
- - 7.4 ps
Table 12. HPD characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage HPD_SINK
[1]
2.0 5.0 5.3 V
V
IL
LOW-level input voltage HPD_SINK 0 - 0.8 V
I
LI
input leakage current HPD_SINK - - 15 µA
V
OH
HIGH-level output voltage HPD_SOURCE 2.5 - V
DD
V
V
OL
LOW-level output voltage HPD_SOURCE 0 - 0.2 V
t
PD
propagation delay from HPD_SINK to HPD_SOURCE;
50 % to 50 %
[2]
- - 200 ns
t
t
transition time HPD_SOURCE rise/fall; 10 % to 90 %
[3]
1 - 20 ns
R
pd
pull-down resistance HPD_SINK input pull-down resistor
[4]
100 200 300 kΩ
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

PTN3361BBS,518

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Buy PTN3361BBS,518
Manufacturer:
NXP Semiconductors
Description:
Buffers & Line Drivers IC LEVEL SHIFTER
Lifecycle:
New from this manufacturer.
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