13
Package Characteristics
Over recommended temperature (T
A
= 0°C to 25°C) unless otherwise specied.
Parameter Symbol Device Min. Typ.* Max. Units Test Conditions Figure Note
Input-Output
Momentary
Withstand
Voltage†
V
ISO
HCPL-4504
HCPL-0454
3750 V rms RH ≤50%,
t = 1 min.,
T
A
= 25°C
6, 13,
16
HCPL-J454 3750 6, 14,
16
HCPL-4504
Option 020
5000 6, 11,
15
HCNW4504 5000 6, 15,
16
Input-Output
Resistance
R
I-O
HCPL-4504
HCPL-0454
HCPL-J454
10
12
Ω V
I-O
= 500 Vdc 6
HCNW4504 10
12
10
13
T
A
= 25°C
10
11
T
A
= 100°C
Capacitance
(Input-Output)
C
I-O
HCPL-4504
HCPL-0454
0.6 pF f = 1 MHz 6
HCPL-J454 0.8
HCNW4504 0.5 0.6
All typicals at T
A
= 25°C..
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable), your
equipment level safety specication or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5. CURRENT TRANSFER RATIO in percent is dened as the ratio of output collector current, I
O
, to the forward LED input current, I
F
, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV
CM
/dt on
the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a Logic High state (i.e., V
O
> 2.0 V). Common mode
transient immunity in a Logic Low level is the maximum tolerable (negative) dV
CM
/dt on the trailing edge of the common mode pulse signal,
V
CM
, to assure that the output will remain in a Logic Low state (i.e., V
O
< 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum
tolerable dV
CM
/dt on the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a Logic High state (i.e., V
O
> 3.0
V). Common mode transient immunity in a Logic Low level is the maximum tolerable dV
CM
/dt on the trailing edge of the common mode pulse
signal, V
CM
, to assure that the output will remain in a Logic Low state (i.e., V
O
< 1.0 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The R
L
= 20 kΩ, C
L
= 100 pF load represents an IPM (Intelligent Power Module) load.
11. See Option 020 data sheet for more information.
12. Use of a 0.1 µF bypass capacitor connected between Pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection
current limit, I
i-o
≤5 µA).
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection
current limit, I
i-o
≤ 5 µA).
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second (leakage detection
current limit, I
i-o
≤5 µA).
16. This test is performed before the 100% Production test shown in the VDE 0884 Insulation Related Characteristics Table, if applicable.
17. The dierence between t
PLH
and t
PHL
between any two devices (same part number) under the same test condition. (See Power Inverter Dead
Time and Propagation Delay Specications section.)
