WM1824 Production Data
w
PD, Rev 4.1, December 2011
22
IMPORTANT NOTICE
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Production Data WM1824
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PD, Rev 4.1, December 2011
23
REVISION HISTORY
DATE REV ORIGINATOR CHANGES PAGE
24/03/10 3.1/
4.0
BT
Removed MCLK Jitter Spec in System Clock Timing table, page 8
BT
Removed maximum line load from electrical characteristics
BT
Updated power state diagram to show all transitions, page 15
BT
Added note in Power up and down control section to recommend
putting the device in standby mode if more than 1 sample rate change
occurs in 1026 LRCLK cycles, page 15
BT
Added reference to WTN0302 in Power up and down control section,
page 15
BT
Added paragraph in Digital Audio Data Sampling Rates section to
recommend putting the device in standby or off mode if more than 1
sample rate change occurs in 1026 LRCLK cycles, page 13
BT
Changed RC value of recommended output filter 20
BT
Added 100 minimum load impedance to prevent over-current
shutdown note to electrical characteristics table
6
24/11/10 4.0 JMacD
Updated to Production Data status
05/12/12 4.1 JMacD
Order codes changed from WM1824GEFL/R and WM1824GEFL/RV
to WM1824CGEFL/R and WM1824CGEFL/RV to reflect change to
copper wire bonding.
3
15/12/12 4.1 JMacD
Relevant Application Note section updated 20

WM1824CGEFL/V

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs Stereo DAC w/ 2Vrms ground ref line Dvr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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