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REEDS-ENCO-E2-N1

P1-P3P4-P6P7-P9P10-P12P13-P15
Lattice Semiconductor Reed-Solomon Encoder User’s Guide
10
A simulation script file is provided in the “eval” directory for RTL simulation. The script file eval_sim_rsenc.do uses
pre-compiled models provided with this package. The pre-compiled library of models is located in the directory
reeds_enco_o4_1_00x/orca4/ver1.3/lib/modelsim/work.
Simulation Procedures:
1. Launch ModelSim
2. Using the main GUI, change the directory location:
Select: File -> Change Directory -> reeds_enco_o4_1_00x/orca4/ver1.3/eval/simulation
3. Execute <Modelsim macro name>.do
Select: Macro -> Execute Macro -> scripts/eval_sim_rsenc.do
The functional simulation for IP cores is currently not applicable with the OEM version of ModelSim embedded in
the ispLEVER 3.0 software. For more information on how to use ModelSim, please refer to the ModelSim User’s
Manual.
Core Implementation
Users can instantiate the IP core to implement it into their system design. The following Verilog source files for
Reed-Solomon Encoder core are provided:
• reeds_enco_o4_1_00x.v for the Reed-Solomon Encoder core-top RTL source
• top_rsenc_pll.v for top-level source
Users can use the core-top RTL as a black box to the system designs. All default signal names in the top-level RTL
source file must be replaced with real signal names from the system design.
Black Box Consideration
Since the core is delivered as a gate-level netlist, the synthesis software will not re-synthesize the internal nets of
the core. In the synthesis process, the instantiated core must be declared as a black box. The ispLEVER software
automatically detects the provided netlist of the instantiated IP core in the design. For more detailed information
regarding Synplify’s black box declaration, please refer to the Instantiating Black Boxes in Verilog section of the
Synplify reference manual.
The core implementation consists of synthesis and place and route sections. Each of the sections is described
below.
Two synthesis tools, Synplicity
®
Synplify
®
and LeonardoSpectrum™, are included in the ispLEVER software for
seamless processing of designs. The current IP cores are being tested with EDIF flow. The following are the step-
by-step procedure for each synthesis tool to generate an EDIF netlist containing the IP core as a black box.
Synthesis Using Synplicity Synplify
The step-by-step procedure below describes how to run synthesis using Synplify outside the ispLEVER Project
Navigator.
1. Create a new working directory for synthesis.
2. Launch the Synplify synthesis tool.
3. Start a new project and add the specified files in the following order:
~/source/reeds_enco_o4_1_00x_params.v
~/source/orca4_synplify.v
~/source/pll_orca.v
~/source/reeds_enco_o4_1_00x.v
~/source/<top-level RTL source>.v
Lattice Semiconductor Reed-Solomon Encoder User’s Guide
11
Note: <top-level RTL source> could be the user’s top-level design or the top-level source (top_rsenc_pll.v) file
in the source directory of the downloaded package.
4. In the Implementation Options, select a target device 4E02, speed grade -2 and package BA352.
5. Specify an EDIF netlist filename and EDIF netlist output location in the Implementation Options. This top-level
EDIF netlist will be used during place and route.
6. Be sure the IP core (reeds_enco_o4_1_00x) is instantiated inside top-level RTL source file.
7. In the Implementation Options, set the following:
• Fanout guide: 500
• Enable FSM compiler
• Enable resource sharing
• Set the global frequency constraint to 195MHz.
8. Select Run.
Synthesis Using LeonardoSpectrum
The step-by-step procedure provided below describes how to run synthesis using LeondardoSpectrum outside the
ispLEVER Project Navigator.
1. Create a new working directory for synthesis.
2. Launch the LeonardoSpectrum synthesis tool.
3. Start a new project and select Lattice device technology ORCA-4E.
4. Set the source directory as the working directory.
5. Open the specified files in the following order:
~/source/reeds_enco_o4_1_00x_params.v
~/source/<top-level RTL source>.v
~/source/pll_orca.v
~/source/reeds_enco_o4_1_00x.v
Note: <top-level RTL source> could be users’ top-level design or the top-level source (top_rsenc_pll.v) file in
the source directory of the downloaded package.
6. Set the synthesis directory, created in step 1, as the path where you would like to save the output netlist.
7. Specify an EDIF netlist filename for the output file. This top-level EDIF netlist will be used during place and
route.
8. Be sure the IP core (reeds_enco_o4_1_00x) is instantiated inside top-level RTL source file.
9. Select Run Flow.
Place and Route
Once the EDIF netlist is generated, the next step is to import the EDIF into the Project Navigator. The step-by-step
procedure provided below describes how to perform place and route in ispLEVER for an ORCA
®
device:
1. Create a new working directory for place and route.
2. Start a new project, assign a project name and select the project type as EDIF.
3. Select an ORCA target device, with -2 speed grade and BA352 package.
Lattice Semiconductor Reed-Solomon Encoder User’s Guide
12
4. Copy the following files to the place and route working directory:
a) ..\..\par\reeds_enco_o4_1_00x.ngo
b) ..\..\par\reeds_enco_o4_1_00x.prf
c) The top-level EDIF netlist generated from running synthesis
5. Rename the reeds_enco_o4_1_00x.prf file (in step 4) to match the project name. For example, if the project
name is “demo”, then the .prf file must be renamed to demo.prf. The preference file name must match that of
the project name.
6. Import the EDIF netlist into the project.
7. In the ispLEVER Project Navigator, select Tools->Timing Checkpoint Options. The Timing Checkpoint Options
window will pop-up. In both Checkpoint Options, select Continue.
8. In the ispLEVER Project Navigator, highlight Place & Route Design, with a right mouse click select Properties.
Set the following Properties:
• Placement Iterations: 1
• Placement Save Best Run: 1
• Placement Iteration Start Point: 20
• Routing Resource Optimization: 5
• Routing Delay Reduction Passes: 2
• Routing Passes: 15
• Placement Effort Level: 5
All other options remain at their default values. The properties shown above are the settings for OC192 mode.
Each configuration has its own properties settings. For the appropriate settings for specific configuration,
please refer to the readme.htm that located in the downloaded package.
9. Select the Place & Route Trace Report in the Project Navigator to execute Place and Route and generate a
timing report for ORCA.
10. If the f
MAX
for the core does not meet the required static timing, then proceed to step 11. Otherwise, jump to
step 13.
11. Select the Cycle Stealing process in the Project Navigator.
12. Select the Place & Route Trace Report process again to generate a new timing report. The Timing Summary
section should indicate no timing errors.
13. When you open the timing report, it is possible you might see some timing violations due to over-constraint. Do
the following steps to obtain a correct timing report:
• Copy the file post_route_trace.prf that is located in directory ~/reeds_enco_o4_1_00x/orca4/ver1.0/par
to the place and route working directory in step 1.
• Open a DOS-shell and change its directory to the working directory in step 1.
• Type: trce -v 1 -c -o post_route_trace.twr <your project_name>.ncd post_route_trace.prf
• The new timing report is generated in post_route_trace.twr
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
P1-P3P4-P6P7-P9P10-P12P13-P15

REEDS-ENCO-E2-N1

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Description:
Development Software Reed Solomon Encoder
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