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REEDS-ENCO-E2-N1

P1-P3P4-P6P7-P9P10-P12P13-P15
Lattice Semiconductor Reed-Solomon Encoder User’s Guide
4
Figure 3 shows the timing of an RS (7,3) single pipelined encoder with
byp
asserted during the operation of the
encoder. The handshaking signals are identical to normal operation, but the output is shifted due to the extra
bypass data, which does not require check symbols.
Figure 3. Timing of an RS (7,3) Single Pipelined Encoder with
byp
Asserted
Figure 4 explains the timing of an RS (7,3) single pipelined encoder with enable de-asserted during the operation
of the encoder. The handshaking signal,
dvalid
, indicates the data on
d_out
is invalid while the encoder main-
tains its state during the time enable is low.
Figure 4. Timing of an RS (7,3) Single Pipelined Encoder with
enable
De-asserted
clk
rstn
start
enable
byp
d_in
d_out
status
rdy
dvalid
D6 D5 D4
D6 D5 D4 C3 C2 C1 C0
DN6 DN5DBP
DBP
XX X3 X2 X1 X0
d_in
D6 D5 D4 DN5DN6
clk
rstn
start
enable
byp
d_out
status
rdy
dvalid
D6 D5 D4 C3 C2 C1 C0D4
Lattice Semiconductor Reed-Solomon Encoder User’s Guide
5
Figure 5 explains the timing of an RS (7,3) single pipelined encoder with start re-asserted during the operation of
the encoder. The handshaking signal,
rdy
, indicates the encoder is ready to receive a new set of data when start is
re-asserted during encoding.
Figure 5. Timing of an RS (7,3) Single Pipelined Encoder with
start
Re-asserted
Figure 6 illustrates the timing of an RS (7,3) double-pipelined encoder during normal operation. The handshake
signals,
status
,
rdy
, and
dvalid
, display how the encoder communicates with the source and destination
devices.
Figure 6. Timing of an RS (7,3) Double Pipelined Encoder
X3 X2 X1X3
clk
rstn
start
enable
byp
d_in
D6 D5 D4
d_out
D6 D5 D4 D6 D5 D4 C3C3
status
rdy
dvalid
D6 D5 D4
X3
clk
rstn
start
enable
byp
X2 X1 X0
d_in
D6 D5 D4 DN5 DN4DN6
d_out
D6 D5 D4 C2 C1 C0C3
status
rdy
dvalid
Lattice Semiconductor Reed-Solomon Encoder User’s Guide
6
Figure 7 shows the timing of an RS (7,3) double-pipelined encoder with
byp
asserted during the operation of the
encoder. The handshaking signals are identical to normal operation, but the output is shifted due to the extra
bypass data, which does not require check symbols.
Figure 7. Timing of an RS (7,3) Double Pipelined Encoder with
byp
Asserted
Figure 8 explains the timing of an RS (7,3) double-pipelined encoder with
enable
de-asserted during the opera-
tion of the encoder. The handshaking signal,
dvalid
, indicates the data on
d_out
is invalid while the encoder
maintains its state during the time enable is low.
Figure 8. Timing of an RS (7,3) Double Pipelined Encoder with
enable
De-asserted
X0X3 X2 X1
clk
rstn
start
enable
byp
d_in
d_out
status
rdy
dvalid
D6 D5 D4
D6 D5 D4 C3 C2 C1
DN6 DN5DBP
DBP
XX X3 X2 X1 X0
d_in
D6 D5 D4 DN5DN6
clk
rstn
start
enable
byp
d_out
status
rdy
dvalid
D6 D5 D4 C3 C2 C1D4
P1-P3P4-P6P7-P9P10-P12P13-P15

REEDS-ENCO-E2-N1

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Buy REEDS-ENCO-E2-N1
Manufacturer:
Lattice
Description:
Development Software Reed Solomon Encoder
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