Lattice Semiconductor Reed-Solomon Encoder User’s Guide
7
Figure 9 explains the timing of an RS (7,3) double-pipelined encoder with
start
re-asserted during the operation
of the encoder. The handshaking signal,
rdy
, indicates the encoder is ready to receive a new set of data when
start
is re-asserted during encoding.
Figure 9. Timing of an RS (7,3) Double Pipelined Encoder with
start
Re-asserted
Signal Definitions
Table 1 shows the input and output signals for the Reed-Solomon Encoder core. Refer to the
ispLEVER™ Software
User’s Manual
for additional information.
Table 1. Reed-Solomon Encoder Signals
Signal Name I/O Type
Active
State
Signal Description
d_in[s-1:0]
Input
N/A Input data
rstn
Input
Low Asynchronous reset input
enable
Input
High Enables the encoder to process data on
d_in
. When low, the input data is
ignored and
d_out
holds its state.
byp
Input
High Indicates the data on
d_in
should pass directly through to
d_out
after the
latency. This signal is ignored if
enable
is low.
start
Input High Indicates that the data on
d_in
is the first information symbol of a new code-
word.This signal is ignored if
byp
is high or enable is low.
clk
Input
Rising Edge Master clock input
d_out[s-1:0]
Output
N/A Output data
status
Output
High Indicates the information symbols are present on
d_out
or
byp
is asserted.
dvalid
Output
High Indicates valid data on
d_out
.Not available with continuous configuration
rdy
Output
High Indicates the encoder is ready to receive data.Active when
rstn
is asserted or
when ready to receive data or
start
is asserted. Inactive when sufficient data
has been received and check symbols are being calculated. Not available with
continuous configuration
X3 X2 X1X3
clk
rstn
start
enable
byp
d_in
D6 D5 D4
d_out
D6 D5 D4 D6 D5 D4C3
status
rdy
dvalid
D6 D5 D4
Lattice Semiconductor Reed-Solomon Encoder User’s Guide
8
Reed-Solomon Encoder Parameters
The Reed-Solomon Encoder has several parameters that allow the core to be configured in different modes listed
in Table 2. Table 3 lists the default field polynomial for a given symbol width.
Table 2. Reed-Solomon Encoder Parameter Descriptions
Table 3. Reed-Solomon Encoder Default Field Polynomial
Name Value Default Description
n 3 - 4095 255 Number of symbols.
k 1 - 4093 239 Number of information symbols.
s 3 - 12 8 Symbol width.
f 11 - 8191 See Table 3 Decimal value of the field polynomial.
rootspace 1 - 65535 1 Root spacing of the generator polynomial. The value of rootspace must satisfy the
following equation: GCD(rootspace, 2
S
-1) = 1. GCD is Greatest Common Divisor.
gstart 0 - 65535 0 Offset value of the generator polynomial. The starting value for the first root of the
generator polynomial is calculated as rootspace * gstart.
inreg 0, 1 1 0 = the inputs will not be registered
1 = the inputs will be registered
latency 2, 3 3 2 = the input on d_in will take 2 clock cycles to reach d_out
3 = the input on d_in will take 3 clock cycles to reach d_out
algorithm 0, 1 1 Selects between two different multiplication algorithms. Used to improve timing
results
handshake 0, 1 0 1 = the core will be a non-continuous core configuration
0 = the core will be a continuous core configuration
(rdy and dvalid will be used in non-continuous configuration only)
Symbol Width Default Field Polynomial Decimal Value
3 x
3
+ x + 1 11
4 x
4
+ x + 1 19
5 x
5
+ x
2
+1 37
6 x
6
+ x + 1 67
7 x
7
+ x
3
+ 1 137
8 x
8
+ x
4
+ x
3
+ x
2
+ 1 285
9 x
9
+ x
4
+ 1 529
10 x
10
+ x
3
+ 1 1033
11 x
11
+ x
2
+ 1 2053
12 x
12
+ x
6
+ x
4
+ x + 1 4179
Lattice Semiconductor Reed-Solomon Encoder User’s Guide
9
Reed-Solomon Encoder Core Design Flow
The Reed-Solomon IP Core can be implemented using various methods. The scope of this document covers only
the push-button Graphical User Interface (GUI) flow. Figure 10 illustrates the software flow model used when
designing with the Reed-Solomon Encoder core.
Figure 10. Lattice IP Core Implementation Flow
IPexpress™
The Lattice IP configuration tool, IPexpress, is incorporated in the ispLEVER
®
software. IPexpress includes a GUI
for entering the required parameters to configure the core. For more information on using IPexpress and the
ispLEVER design software, refer to the software help and tutorials included with ispLEVER. For more information
on ispLEVER, see the Lattice web site at www.latticesemi.com/software.
Functional RTL Simulation Under ModelSim (PC Platform)
Once the Reed-Solomon Encoder core has been downloaded and unzipped to the designated directory, the core is
ready for evaluation. The functional simulation of the RS Encoder core involved developing a verification environ-
ment that supports a very comprehensive test suite.
Install and launch ispLEVER software
IP Core Netlist
Start
Protected
Simulation
Model
Obtain desired IP package (download
Core Evaluation package or purchase
IP package)
Install IP package
Perform functional simulation with
the provided core model
Synthesize top-level design with the
IP black box declaration
Place and route the design
Run static timing analysis
Done
Note: The following procedures are shown using the ORCA
®
Series 4 version of the Reed-Solomon Decoder
core. For other device versions, refer to the Readme release notes included in that evaluation package.

REEDS-ENCO-E2-N1

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Lattice
Description:
Development Software Reed Solomon Encoder
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