AD5320BRTZ-500RL7 Datasheet AD5320BRTZ-REEL7, AD5320BRTZ-500RL7, AD5320BRMZ-REEL7 | P13-P15

AD5320

Rev. C | Page 12 of 20

SERIAL INTERFACE

The AD5320 has a 3-wire serial interface (

SYNC

, SCLK, and

DIN) that is compatible with SPI®, QSPI

, and

MICROWIRE

interface standards as well as most DSPs. See

Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the

SYNC

line low. Data

from the DIN line is clocked into the 16-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 30 MHz, making the AD5320 compatible with high speed

DSPs. On the 16th falling clock edge, the last data bit is clocked

in and the programmed function is executed (that is, a change

in DAC register contents and/or a change in the mode of

operation). At this stage, the

SYNC

line can be kept low or be

brought high. In either case, it must be brought high for a

minimum of 33 ns before the next write sequence so that a

falling edge of

SYNC

can initiate the next write sequence.

Because the

SYNC

buffer draws more current when V

= 2.4 V

than it does when V

= 0.8 V,

SYNC

should be idled low

between write sequences for even lower power operation of the

part. As previously mentioned,

SYNC

must be brought high

again just before the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide (see Figure 25). The first two

bits are “don’t cares.” The next two are control bits that control

which mode of operation the part is in (normal mode or any one of

three power-down modes). There is a more complete description of

the various modes in the Power-Down Modes section. The next

twelve bits are the data bits. These are transferred to the DAC

SYNC INTERRUPT

In a normal write sequence, the

SYNC

line is kept low for at

least 16 falling edges of SCLK and the DAC is updated on the

16th falling edge. However, if

SYNC

is brought high before the

16th falling edge, then this acts as an interrupt to the write

sequence. The shift register is reset and the write sequence is

seen as invalid. Neither an update of the DAC register contents

nor a change in the operating mode occurs (see

Figure 26).

POWER-ON RESET

The AD5320 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

zeros and the output voltage is 0 V. It remains there until a valid

write sequence is made to the DAC. This is useful in applica-

tions where it is important to know the state of the output of the

DAC while it is in the process of powering up.

DB15 (MSB) DB0 (LSB)

X PD0 D11 D10 D9 D8 D7 D6 D5 D4PD1X D3 D2 D1 D0

DATA BITS

00934-025

NORMAL OPERATION

1kΩ TO GND

100kΩ TO GND

THREE–STATE

POWER-DOWN MODES

Figure 25. Input Register Contents

DB15 DB0 DB15

SCLK

YNC

DIN

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 16TH FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 16TH FALLING EDGE

DB0

00934-028

Figure 26.

SYNC

Interrupt Facility

AD5320

Rev. C | Page 13 of 20

POWER-DOWN MODES

The AD5320 contains four separate modes of operation. These

modes are software-programmable by setting two bits (DB13

and DB12) in the control register.

Tabl e 5 shows how the state

of the bits corresponds to the mode of operation of the device.

Table 5. Modes of Operation for the AD5320

DB13 DB12 Operating Mode

0 0 Normal Operation

Power-Down Modes

0 1 1 kΩ to GND

1 0 100 kΩ to GND

1 1 Three-State

When both bits are set to 0, the part works with its normal power

consumption of 140 μA at 5 V. However, for the three power-down

modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not

only does the supply current fall, but the output stage is also inter-

nally switched from the output of the amplifier to a resistor net-

work of known values. This has the advantage that the output

impedance of the part is known while the part is in power-down

mode. There are three different options: the output is connected

internally to GND through a 1 kΩ resistor, the output is connected

internally to GND through a 100 kΩ resistor, or it is left open-

circuited (three-state). The output stage is illustrated in

Figure 27.

RESISTOR

STRING DAC

RESISTOR

NETWORK

POWER-DOWN

CIRCUITRY

OUT

00934-026

AMPLIFIER

Figure 27. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when the power-down

mode is activated. However, the contents of the DAC register

are unaffected when in power-down. The time to exit power-

down is typically 2.5 μs for V

= 5 V and 5 μs for V

= 3 V

(see

Figure 21).

AD5320

Rev. C | Page 14 of 20

MICROPROCESSOR INTERFACING

AD5320 TO ADSP-2101/ADSP-2103 INTERFACE

Figure 28 shows a serial interface between the AD5320 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in the serial port (SPORT) transmit alter-

nate framing mode. The ADSP-2101/ADSP-2103 SPORT are

programmed through the SPORT control register and should

be configured as follows: internal clock operation, active low

framing, and 16-bit word length. Transmission is initiated by

writing a word to the Tx register after the SPORT has been

enabled.

AD5320 TO 68HC11/68L11 INTERFACE

Figure 29 shows a serial interface between the AD5320 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the AD5320, while the MOSI output drives

the serial data line of the DAC. The

SYNC

signal is derived

from a port line (PC7). For correct operation of this interface,

the 68HC11/68L11 should be configured so that the CPOL bit

is a 0 and the CPHA bit is a 1. When data is being transmitted

to the DAC, the

SYNC

line is taken low (PC7). When the

68HC11/68L11 are configured, data appearing on the MOSI

output is valid on the falling edge of SCK as shown in Figure 29.

Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes

with only eight falling clock edges occurring in the transmit

cycle. Data is transmitted MSB first. In order to load data to the

AD5320, PC7 is left low after the first eight bits are transferred,

and a second serial write operation is performed to the DAC

and PC7 is taken high at the end of this procedure.

DIN

SCLK

SYNC

PC7

SCK

MOSI

68HC11/68L11*

*ADDITIONAL PINS OMITTED FOR CLARITY

00934-029

AD5320*

Figure 29. AD5320 to 68HC11/68L11 Interface

AD5320 TO 80C51/80L51 INTERFACE

Figure 30 shows a serial interface between the AD5320 and the

80C51/80L51 microcontrollers. TXD of the 80C51/80L51 drives

SCLK of the AD5320, while RXD drives the serial data line of

the part. The

SYNC

signal is again derived from a bit

programmable pin on the port. In this case, port line P3.3 is

used. When data is to be transmitted to the AD5320, P3.3 is

taken low. The 80C51/80L51 transmits data only in 8-bit bytes;

thus only eight falling clock edges occur in the transmit cycle.

To load data to the DAC, P3.3 is left low after the first eight bits

are transmitted, and a second write cycle is initiated to transmit

the second byte of data. P3.3 is taken high following the

completion of this cycle. The 80C51/ 80L51 output the serial

data in a format that has the LSB first. The AD5320 requires its

data with the MSB as the first bit received. The 80C51/80L51

transmit routine should consider this.

DIN

SCLK

SYNC

P3.3

TXD

RXD

80C51/80L51*

*ADDITIONAL PINS OMITTED FOR CLARITY

00934-030

AD5320*

Figure 30. AD5320 to 80C51/80L51 Interface

AD5320 TO MICROWIRE INTERFACE

Figure 31 shows an interface between the AD5320 and any

MICROWIRE-compatible device. Serial data is shifted out on

the falling edge of the serial clock and is clocked into the

AD5320 on the rising edge of the SK.

DIN

SCLK

SYNC

MICROWIRE*

*ADDITIONAL PINS OMITTED FOR CLARITY

00934-031

AD5320*

Figure 31. AD5320 to MICROWIRE Interface

SCLK

DIN

SYNC

TFS

SCLK

ADSP-2101/

ADSP-2103*

*ADDITIONAL PINS OMITTED FOR CLARITY

00934-027

AD5320*

Figure 28. AD5320 to ADSP-2101/ADSP-2103 Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD5320BRTZ-500RL7

Mfr. #:

Buy AD5320BRTZ-500RL7

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 12 Bit Vout 8uS

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD5320BRTZ-500RL7

AD5320BRTZ-500RL7

Products related to this Datasheet