AD5320
Rev. C | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5320
TOP VIEW
(Not to Scale)
V
OUT
1
GND
2
V
DD
3
SYNC
SCLK
DIN
6
5
4
00934-003
Figure 3. SOT-23 Pin Configuration
AD5320
TOP VIEW
(Not to Scale)
V
DD
1
NC
2
NC
3
V
OUT
4
SYNC
SCLK
DIN
GND
8
7
6
5
00934-004
NC = NO CONNECT
Figure 4. MSOP Pin Configuration
Table 4. Pin Function Descriptions
SOT-23
Pin No.
MSOP
Pin No.
Mnemonic
Description
1 4 V
OUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
2 8 GND Ground Reference Point for All Circuitry on the Part.
3 1 V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and V
DD
should be decoupled
to GND.
4 7 DIN
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
5 6 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
6 5
SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When
SYNC goes low, it enables the input shift register and data is transferred in on the falling edges
of the following clocks. The DAC is updated following the 16th clock cycle unless
SYNC is taken high
before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the DAC.
2, 3 NC No Connect.
AD5320
Rev. C | Page 7 of 20
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in
Figure 5.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in
Figure 6.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (000 hex) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5320 because the output of the DAC cannot go below 0 V
due to a combination of the offset errors in the DAC and output
amplifier. Zero-code error is expressed in mV. A plot of zero-
code error vs. temperature can be seen in
Figure 9.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (FFF Hex) is loaded to the DAC register. Ideally the output
should be V
DD
− 1 LSB. Full-scale error is expressed in percent
of full-scale range. A plot of full-scale error vs. temperature can
be seen in
Figure 9.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Total Unadjuste d Error
Total unadjusted error (TUE) is a measure of the output error
considering all the various errors. A typical TUE vs. code plot
can be seen in
Figure 7.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV
seconds and is measured when the digital input code is changed
by 1 LSB at the major carry transition (7FF Hex to 800 Hex); see
Figure 22.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It
is specified in nV seconds and measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa.
AD5320
Rev. C | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
INL @ 5V
INL @ 3V
CODE
INL ERROR (LSBs)
16
12
4
–4
–12
8
0
–8
–16
0 800 1600 2400 40003200
00934-005
T
A
= 25°C
Figure 5. Typical INL Plot
CODE
DNL ERROR (LSBs)
1.0
0.5
0
–0.5
–1.0
0 1000 2000 3000 4000
00934-006
DNL @ 3V
DNL @ 5V
T
A
= 25°C
Figure 6. Typical DNL Plot
CODE
TUE (LSBs)
16
8
0
–8
–16
0 800 1600 2400 40003200
00934-007
TUE @ 3V
TUE @ 5V
T
A
= 25°C
Figure 7. Typical Total Unadjusted Error Plot
MAX INL
MAX DNL
MIN INL
MIN DNL
TEMPERATURE (°C)
–40 0 40 80 120
00934-008
16
12
4
–4
–12
8
0
–8
–16
ERROR (LSBs)
Figure 8. INL Error and DNL Error vs. Temperature
V
DD
= 5V
ZS ERROR
FS ERROR
30
20
30
0
10
20
10
TEMPERATURE (°C)
ERROR (mV)
–40 0 40 80 120
00934-009
Figure 9. Zero-Scale Error and Full-Scale Error vs. Temperature
2500
2000
500
50 190
1500
1000
0
FREQUENCY
V
DD
= 3V
V
DD
= 5V
60 70 80 90 100 110 120 130 140 150 160 170 180
00934-010
I
DD
(µA)
Figure 10. I
DD
Histogram with V
DD
= 3 V and V
DD
= 5 V

AD5320BRTZ-500RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12 Bit Vout 8uS
Lifecycle:
New from this manufacturer.
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