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AD420ARZ-32

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Data Sheet AD420
THEORY OF OPERATION
The AD420 uses a sigma-delta (Σ-Δ) architecture to carry out
the digital-to-analog conversion. This architecture is particularly
well suited for the relatively low bandwidth requirements of the
industrial control environment because of its inherent
monotonicity at high resolution.
In the AD420 a second order modulator is used to keep com-
plexity and die size to a minimum. The single bit stream from
the modulator controls a switched current source that is then
filtered by two, continuous time resistor-capacitor sections.
The capacitors are the only external components that have to be
added for standard current-out operation. The filtered current
is amplified and mirrored to the supply rail so that the application
simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA
current source output with respect to ground. The AD420
is manufactured on a BiCMOS process that is well suited to
implementing low voltage digital logic with high performance
and high voltage analog circuitry.
The AD420 can also provide a voltage output instead of a current
loop output if desired. The addition of a single external amplifier
allows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or ±10 V.
The AD420 has a loop fault detection circuit that warns if the
voltage at I
OUT
attempts to rise above the compliance range, due
to an open-loop circuit or insufficient power supply voltage. The
FAULT DETECT is an active low open drain signal so that one
can connect several AD420s together to one pull-up resistor for
global error detection. The pull-up resistor can be tied to the
V
LL
pin, or an external +5 V logic supply.
The I
OUT
current is controlled by a PMOS transistor and an
internal amplifier as shown in the functional block diagram.
The internal circuitry that develops the fault output avoids
using a comparator with window limits since this would require
an actual output error before the FAULT DETECT output
becomes active. Instead, the signal is generated when the
internal amplifier in the output stage of the AD420 has less than
approximately one volt remaining of drive capability (when
the gate of the output PMOS transistor nearly reaches ground).
Thus the FAULT DETECT output activates slightly before the
compliance limit is reached. Since the comparison is made
within the feedback loop of the output amplifier, the output
accuracy is maintained by its open-loop gain, and no output
error occurs before the fault detect output becomes active.
The 3-wire digital interface, comprising DATA IN, CLOCK,
and LATCH, interfaces to all commonly used serial micropro-
cessors without the addition of any external glue logic. Data is
loaded into an input register under control of CLOCK and is
loaded to the DAC when LATCH is strobed. If a user wants to
minimize the number of galvanic isolators in an intrinsically
safe application, the AD420 can be configured to run in
asynchronous mode. This mode is selected by connecting the
LATCH pin to V
CC
through a current limiting resistor. The data
must then be combined with a start and stop bit to frame the
information and trigger the internal LATCH signal.
FAU
LT
DETECT
I
OUT
BOOST
40Ω
1.25kΩ
4kΩ
V
OUT
OFFSET
TRIM
CAP 1 CAP 2 GND
V
L
L
V
CC
REF OUT
REF IN
DAT
A
OUT
CLEAR
LA
TCH
CLOCK
DAT
A
IN
RANGE
SELECT 1
RANGE
SELECT 2
AD420
REFERENCE
DATA I/P
REGISTER
SWITCHED
CURRENT
SOURCES
AND
FI
LTERING
CLOCK
16-BIT
DAC
00494-005
2
19
23
18
17
3
21 11
2016
14
15
10
6
7
8
9
5
4
Figure 5. Functional Block Diagram
Rev. I | Page 9 of 16
AD420 Data Sheet
APPLICATIONS INFORMATION
CURRENT OUTPUT
The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA–
24 mA output without any active external components. Filter
capacitors C1 and C2 can be any type of low cost ceramic
capacitors. To meet the specified full-scale settling time of 3 ms,
low dielectric absorption capacitors (NPO) are required.
Suitable values are C1 = 0.01 µF and C2 = 0.01 µF.
00494-006
5
2 20
14 15
11
21 23
4
6
18
7
8
9
I
OUT
(4m
A
T
O 20mA)
R
LOAD
V
CC
V
LL
AD420
GND
0.1µF0.1µF
REF IN
REF OUT
C1
C2
D
ATA
IN
CLOCK
L
ATCH
CLEAR
RANGE
SELECT 2
RANGE
SELECT 1
Figure 6. Standard Configuration
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads ,connect a 0.01 µF
capacitor between I
OUT
(Pin 18) and GND (Pin 11). This ensures
stability of the AD420 with loads beyond 50 mH. There is no
maximum capacitance limit. The capacitive component of the
load may cause slower settling, though this may be masked by
the settling time of the AD420. A programmed change in the
current may cause a back EMF voltage on the output that may
exceed the compliance of the AD420. To prevent this voltage
from exceeding the supply rails connect protective diodes
between I
OUT
and each of V
CC
and GND.
VOLTAGE-MODE OUTPUT
Since the AD420 is a single supply device, it is necessary to add
an external buffer amplifier to the V
OUT
pin to obtain a selection
of bipolar output voltage ranges as shown in Figure 7.
00494-007
5
2 20
14
15 11
21
23
4
6 17
7
8
9
V
OUT
V
OUT
R2
R3
R1
V
CC
V
L
L
AD420
GND
0.1µF
0.1µF
REF IN
REF OUT
C1
C2
DATA IN
CLOCK
LA
TCH
CLEAR
RANGE
SELECT 2
RANGE
SELECT 1
Figure 7.
Table 7. Buffer Amplifier Configuration
R1
R2
R3
V
OUT
Open Open 0 0 V − 5 V
Open R R
R Open R ±5 V
R 2R 2R ±10 V
Suitable R = 5 kΩ.
OPTIONAL SPAN AND ZERO TRIM
For users who would like lower than the specified values of
offset and gain error, Figure 8 shows a simple way to trim these
parameters. Care should be taken to select low drift resistors
because they affect the temperature drift performance of
the DAC.
The adjustment algorithm is iterative. The procedure for
trimming the AD420 in the 4 mA–20 mA mode can be
accomplished as follows:
1. Offset adjust. Load all zeros. Adjust RZERO for
4.00000 mA of output current.
2. Gain adjust. Load all ones. Adjust RSPAN for 19.99976 mA
(FS − 1 LSB) of output current.
Return to Step I and iterate until convergence is obtained.
00494-008
5
2 20
14 15 16
11
21
23
4
6
18
19
7
8
9
I
OUT
(4mA TO 20mA)
R
LOAD
5kΩ
RSPAN2
500Ω
RSPAN
10kΩ
RZERO
BOOST
V
CC
AD420
GND
REF OUT
C1 C2
DATA IN
CLOCK
LATCH
CLEAR
RANGE
SELECT 2
RANGE
SELECT 1
V
LL
0.1µF
0.1µF
Figure 8. Offset and Gain Adjust
Variation of RZERO between REF OUT (5 V) and GND leads
to an offset adjust range from −1.5 mA to 6 mA, (1.5 mA/V
centered at 1 V).
The 5 kΩ RSPAN2 resistor is connected in parallel with the
internal 40 W sense resistor, which leads to a gain increase of
+0.8%.
As RSPAN is changed to 500 Ω, the voltage on REF IN is
attenuated by the combination of RSPAN and the 30 kΩ REF IN
input resistance. When added together with RSPAN2 this
results in an adjustment range of −0.8% to +0.8%.
Rev. I | Page 10 of 16
Data Sheet AD420
Rev. I | Page 11 of 16
THREE-WIRE INTERFACE
Figure 9 shows the AD420 connected in the 3-wire interface
mode. The AD420 data input block contains a serial input shift
register and a parallel latch. The contents of the shift register
are controlled by the DATA IN signal and the rising edges of the
CLOCK. Upon request of the LATCH pin the DAC and internal
latch are updated from the shift register parallel outputs. The
CLOCK should remain inactive while the DAC is updated.
Refer to the timing requirements for 3-wire interface.
00494-009
FAULT
DETECT
FAULT DETECT
DATA
IN
CLOCK
GND
LATCH
DATA IN
CLOCK
LATCH
V
CC
R
LOAD
V
CC
I
OUT
DATA
OUT
AD420
DAC1
FAULT
DETECT
DATA
IN
CLOCK
GND
LATCH
V
CC
V
LL
R
LOAD
V
CC
I
OUT
DATA
OUT
AD420
DAC2
10kΩ
Figure 9. Three-Wire Interface Using Multiple DACs with Joint Fault Detect
USING MULTIPLE DACS WITH FAULT DETECT
The 3-wire interface mode can utilize the serial DATA OUT for
easy interface to multiple DACs. To program the two AD420s in
Figure 9, 32 data bits are required. The first 16 bits are clocked
into the input shift register of DAC1. The next 16 bits
transmitted pass the first 16 bits from the DATA OUT pin of
DAC1 to the input register of DAC2. The input shift registers of
the two DACs operate as a single 32-bit shift register, with the
leading 16 bits representing information for DAC2 and the
trailing 16 bits serving for DAC1. Each DAC is then updated
upon request of the LATCH pin. The daisy-chain can be
extended to as many DACs as required.
ASYNCHRONOUS INTERFACE USING
OPTOCOUPLERS
The AD420 connected in asynchronous interface mode with
optocouplers is shown in Figure 10. Asynchronous operation
minimizes the number of control signals required for isolation
of the digital system from the control loop. The resistor connected
between the LATCH pin and V
CC
is required to activate this
mode. For operation with V
CC
below 18 V use a 50 kΩ pull-up
resistor; from 18 V to 32 V, use 100 kΩ.
Asynchronous mode requires that the clock run at 16 times the
data bit rate, therefore, to operate at the maximum input data rate
of 150 kBPS, an input clock of 2.4 MHz is required. The actual
data rate achieved may be limited by the type of optocouplers
chosen. The number of control signals can be further reduced
by creating the appropriate clock signal on the current loop
side of the isolation barrier. If optocouplers with relatively slow
rise and fall times are used, Schmitt triggers may be required on
the digital inputs to prevent erroneous data being presented to
the DAC.
00494-010
8
2
7
23
9
11
V
CC
+24
V
+5V
V
LL
LATCH
100kΩ
AD420
CLOCK
DATA IN
ISOLATION
GALVANIC
BARRIER
CLOCK
DATA
GND
Figure 10. Asynchronous Interface Using Optocouplers
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD420ARZ-32

Mfr. #:
Buy AD420ARZ-32
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC 16-BIT
Lifecycle:
New from this manufacturer.
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