AD420 Data Sheet
MICROPROCESSOR INTERFACE
AD420-TO-MC68HC11 (SPI BUS) INTERFACE
The AD420 interface to the Motorola serial peripheral interface
(SPI) is shown in Figure 11. The MOSI, SCK, and
SS
pins of the
HC11 are respectively connected to the DATA IN, CLOCK, and
LATCH pins of the AD420. The majority of the interfacing
issues are done in the software initialization. A typical routine,
such as the one shown below, begins by initializing the state of
the various SPI data and control registers.
INIT
LDAA
#$2F
;
SS
= 1; SCK = 0;
MOSI = 1
STAA
PORTD
;SEND TO SPI OUTPUTS
LDAA
#$38
;
SS
, SCK, MOSI =
OUTPUTS
STAA
DDRD
;SEND DATA DIRECTION
INFO
LDAA
#$50
;DABL INTRPTS, SPI
IS MASTER & ON
STAA
SPCR
;CPOL = 0, CPHA = 0,
1MHZ BAUDRATE
NEXTPT
LDAA
MSBY
;LOAD ACCUM W/UPPER
8 BITS
BSR
SENDAT
;JUMP TO DAC OUTPUT
ROUTINE
JMP
NEXTPT
;INFINITE LOOP
SENDAT
LDY #$1000
;POINT AT ON-CHIP
REGISTERS
BCLR
$08,Y,$20
;DRIVE
SS
(LATCH)
LOW
STAA
SPDR
;SEND MS-BYTE TO SPI
DATA REG
WAIT1 LDAA
SPSR
;CHECK STATUS OF
SPIE
BPL
WAIT1
;POLL FOR END OF X-
MISSION
LDAA
LSBY
;GET LOW 8 BITS FROM
MEMORY
STAA
SPDR
;SEND LS-BYTE TO SPI
DATA REG
WAIT2
LDAA
SPSR
;CHECK STATUS OF
SPIE
BPL
WAIT2;
;POLL FOR END OF X-
MISSION
BSET
$08,Y,$20
;DRIVE
SS
HIGH TO
LATCH DATA
RTS
The SPI data port is configured to process data in 8-bit bytes.
The most significant data byte (MSBY) is retrieved from
memory and processed by the SENDAT routine. The
SS
pin is
driven low by indexing into the PORTD data register and clear
Bit 5. The MSBY is then sent to the SPI data register where it is
automatically transferred to the AD420 internal shift resister.
The HC11 generates the requisite eight clock pulses with data
valid on the rising edges. After the MSBY is transmitted, the
least significant byte (LSBY) is loaded from memory and
transmitted in a similar fashion. To complete the transfer, the
LATCH pin is driven high when loading the complete 16-bit
word into the AD420.
00494-011
DAT
A IN
CLOCK
LATCH
MOSI
SCK
SS
68HC11
AD420
Figure 11. AD420-to-68HC11 (SPI) Interface
AD420 TO MICROWIRE INTERFACE
The flexible serial interface of the AD420 is also compatible
with the National Semiconductor MICROWIRE interface. The
MICROWIRE interface is used in microcontrollers such as the
COP400 and COP800 series of processors. A generic interface
to use the MICROWIRE interface is shown in Figure 12. The
G1, SK, and SO pins of the MICROWIRE interface are
respectively connected to the LATCH, CLOCK, and DATA IN
pins of the AD420.
00494-012
DATA IN
CLOCK
LATCH
SO
SK
G1
MICROWIRE
AD420
Figure 12. AD420-to-MICROWIRE Interface
Rev. I | Page 12 of 16
Data Sheet AD420
Rev. I | Page 13 of 16
EXTERNAL BOOST FUNCTION
The external boost transistor reduces the power dissipated in
the AD420 by reducing the current flowing in the on-chip
output transistor (dividing it by the current gain of the external
circuit). A discrete NPN transistor with a breakdown voltage,
BV
CEO
, greater than 32 V can be used as shown in Figure 13.
00494-013
AD420
MJD31C
OR
2N3053
19
BOOST
I
OUT
0.022µF
1k
R
LOAD
18
Figure 13. External Boost Configuration
The external boost capability has been developed for those
users who may wish to use the AD420, in the SOIC package, at
the extremes of the supply voltage, load current, and
temperature range. The PDIP package (because of its lower
thermal resistance) will operate safely over the entire specified
voltage, temperature, and load current ranges without the boost
transistor. The plot in Figure 14 shows the safe operating region
for both package types. The boost transistor can also be used to
reduce the amount of temperature induced drift in the part.
This will minimize the temperature induced drift of the on-chip
voltage reference, which improves drift and linearity.
00494-014
28V
20V
12V
4V
–60 –40 –20 0 20 40 60 80 100
TEMPERATUREC)
25V
AD420 OR AD420-32
32V
V
CC
WHEN USING SOIC PACKAGED DEVICES,
AN EXTERNAL BOOST TRANSISTOR IS
REQUIRED FOR OPERATION IN THIS AREA.
Figure 14. Safe Operating Region
AD420 Data Sheet
AD420 PROTECTION
TRANSIENT VOLTAGE PROTECTION
The AD420 contains ESD protection diodes, which prevent
damage from normal handling. The industrial control envir-
onment can, however, subject I/O circuits to much higher
transients. To protect the AD420 from excessively high voltage
transients, such as those specified in IEC 801, external power
diodes and a surge current limiting resistor may be required, as
shown in Figure 15. The constraint on the resistor is that during
normal operation the output voltage level at I
OUT
must remain
within its voltage compliance limit
(I
OUT
× (Rp + R
LOAD
) ≤ V
CC
2.75 V)
and the two protection diodes and resistor must have
appropriate power ratings.
00494-015
AD420
I
OUT
V
CC
V
CC
R
LOAD
R
P
GND
Figure 15. Output Transient Voltage Protection
BOARD LAYOUT AND GROUNDING
The AD420 ground pin, designated GND, is the high quality
ground reference point for the device. Any external loads on the
REF OUT and V
OUT
pins of the AD420 should be returned to
this reference point. Analog and digital ground currents should
not share a common path. Each signal should have an appropriate
analog or digital signal return routed close to it. Using this
approach, signal loops enclose a small area, minimizing the
inductive coupling of noise. Wide PC tracks, large gauge wire,
and ground planes are highly recommended to provide low
impedance signal paths.
POWER SUPPLIES AND DECOUPLING
The AD420 supply pins, V
CC
(Pin 23) and V
LL
(Pin 2), should be
decoupled to GND with 0.1 µF capacitors to eliminate high
frequency noise that may otherwise get coupled into the analog
system. High frequency ceramic capacitors are recommended.
The decoupling capacitors should be located in close proximity
to the pins and the ground line to have maximum effect. Further
reductions in noise, and improvements in performance, may be
achieved by using a larger value capacitor on the V
LL
pin.
Rev. I | Page 14 of 16

AD420ARZ-32

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC 16-BIT
Lifecycle:
New from this manufacturer.
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